arm/mach-ux500/db8500-regs.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (C) ST-Ericsson SA 2010
0004  */
0005
0006 #ifndef __MACH_DB8500_REGS_H
0007 #define __MACH_DB8500_REGS_H
0008
0009 /* Base address and bank offsets for ESRAM */
0010 #define U8500_ESRAM_BASE    0x40000000
0011 #define U8500_ESRAM_BANK_SIZE   0x00020000
0012 #define U8500_ESRAM_BANK0   U8500_ESRAM_BASE
0013 #define U8500_ESRAM_BANK1   (U8500_ESRAM_BASE + U8500_ESRAM_BANK_SIZE)
0014 #define U8500_ESRAM_BANK2   (U8500_ESRAM_BANK1 + U8500_ESRAM_BANK_SIZE)
0015 #define U8500_ESRAM_BANK3   (U8500_ESRAM_BANK2 + U8500_ESRAM_BANK_SIZE)
0016 #define U8500_ESRAM_BANK4   (U8500_ESRAM_BANK3 + U8500_ESRAM_BANK_SIZE)
0017 /*
0018  * on V1 DMA uses 4KB for logical parameters position is right after the 64KB
0019  * reserved for security
0020  */
0021 #define U8500_ESRAM_DMA_LCPA_OFFSET     0x10000
0022
0023 #define U8500_DMA_LCPA_BASE    (U8500_ESRAM_BANK0 + U8500_ESRAM_DMA_LCPA_OFFSET)
0024
0025 /* This address fulfills the 256k alignment requirement of the lcla base */
0026 #define U8500_DMA_LCLA_BASE U8500_ESRAM_BANK4
0027
0028 #define U8500_PER3_BASE     0x80000000
0029 #define U8500_STM_BASE      0x80100000
0030 #define U8500_STM_REG_BASE  (U8500_STM_BASE + 0xF000)
0031 #define U8500_PER2_BASE     0x80110000
0032 #define U8500_PER1_BASE     0x80120000
0033 #define U8500_B2R2_BASE     0x80130000
0034 #define U8500_HSEM_BASE     0x80140000
0035 #define U8500_PER4_BASE     0x80150000
0036 #define U8500_TPIU_BASE     0x80190000
0037 #define U8500_ICN_BASE      0x81000000
0038
0039 #define U8500_BOOT_ROM_BASE 0x90000000
0040 /* ASIC ID is at 0xbf4 offset within this region */
0041 #define U8500_ASIC_ID_BASE  0x9001D000
0042
0043 #define U8500_PER6_BASE     0xa03c0000
0044 #define U8500_PER7_BASE     0xa03d0000
0045 #define U8500_PER5_BASE     0xa03e0000
0046
0047 #define U8500_SVA_BASE      0xa0100000
0048 #define U8500_SIA_BASE      0xa0200000
0049
0050 #define U8500_SGA_BASE      0xa0300000
0051 #define U8500_MCDE_BASE     0xa0350000
0052 #define U8500_DMA_BASE      0x801C0000  /* v1 */
0053
0054 #define U8500_SBAG_BASE     0xa0390000
0055
0056 #define U8500_SCU_BASE      0xa0410000
0057 #define U8500_GIC_CPU_BASE  0xa0410100
0058 #define U8500_TWD_BASE      0xa0410600
0059 #define U8500_GIC_DIST_BASE 0xa0411000
0060 #define U8500_L2CC_BASE     0xa0412000
0061
0062 #define U8500_MODEM_I2C     0xb7e02000
0063
0064 #define U8500_GPIO0_BASE    (U8500_PER1_BASE + 0xE000)
0065 #define U8500_GPIO1_BASE    (U8500_PER3_BASE + 0xE000)
0066 #define U8500_GPIO2_BASE    (U8500_PER2_BASE + 0xE000)
0067 #define U8500_GPIO3_BASE    (U8500_PER5_BASE + 0x1E000)
0068
0069 #define U8500_UART0_BASE    (U8500_PER1_BASE + 0x0000)
0070 #define U8500_UART1_BASE    (U8500_PER1_BASE + 0x1000)
0071
0072 /* per6 base addresses */
0073 #define U8500_RNG_BASE      (U8500_PER6_BASE + 0x0000)
0074 #define U8500_HASH0_BASE        (U8500_PER6_BASE + 0x1000)
0075 #define U8500_HASH1_BASE        (U8500_PER6_BASE + 0x2000)
0076 #define U8500_PKA_BASE      (U8500_PER6_BASE + 0x4000)
0077 #define U8500_PKAM_BASE     (U8500_PER6_BASE + 0x5100)
0078 #define U8500_MTU0_BASE     (U8500_PER6_BASE + 0x6000) /* v1 */
0079 #define U8500_MTU1_BASE     (U8500_PER6_BASE + 0x7000) /* v1 */
0080 #define U8500_CR_BASE       (U8500_PER6_BASE + 0x8000) /* v1 */
0081 #define U8500_CRYP0_BASE    (U8500_PER6_BASE + 0xa000)
0082 #define U8500_CRYP1_BASE    (U8500_PER6_BASE + 0xb000)
0083 #define U8500_CLKRST6_BASE  (U8500_PER6_BASE + 0xf000)
0084
0085 /* per5 base addresses */
0086 #define U8500_USBOTG_BASE   (U8500_PER5_BASE + 0x00000)
0087 #define U8500_CLKRST5_BASE  (U8500_PER5_BASE + 0x1f000)
0088
0089 /* per4 base addresses */
0090 #define U8500_BACKUPRAM0_BASE   (U8500_PER4_BASE + 0x00000)
0091 #define U8500_BACKUPRAM1_BASE   (U8500_PER4_BASE + 0x01000)
0092 #define U8500_RTT0_BASE     (U8500_PER4_BASE + 0x02000)
0093 #define U8500_RTT1_BASE     (U8500_PER4_BASE + 0x03000)
0094 #define U8500_RTC_BASE      (U8500_PER4_BASE + 0x04000)
0095 #define U8500_SCR_BASE      (U8500_PER4_BASE + 0x05000)
0096 #define U8500_DMC_BASE      (U8500_PER4_BASE + 0x06000)
0097 #define U8500_PRCMU_BASE    (U8500_PER4_BASE + 0x07000)
0098 #define U9540_DMC1_BASE     (U8500_PER4_BASE + 0x0A000)
0099 #define U8500_PRCMU_TCDM_BASE   (U8500_PER4_BASE + 0x68000)
0100 #define U8500_PRCMU_TCPM_BASE   (U8500_PER4_BASE + 0x60000)
0101 #define U8500_PRCMU_TIMER_3_BASE (U8500_PER4_BASE + 0x07338)
0102 #define U8500_PRCMU_TIMER_4_BASE (U8500_PER4_BASE + 0x07450)
0103
0104 /* per3 base addresses */
0105 #define U8500_FSMC_BASE     (U8500_PER3_BASE + 0x0000)
0106 #define U8500_SSP0_BASE     (U8500_PER3_BASE + 0x2000)
0107 #define U8500_SSP1_BASE     (U8500_PER3_BASE + 0x3000)
0108 #define U8500_I2C0_BASE     (U8500_PER3_BASE + 0x4000)
0109 #define U8500_SDI2_BASE     (U8500_PER3_BASE + 0x5000)
0110 #define U8500_SKE_BASE      (U8500_PER3_BASE + 0x6000)
0111 #define U8500_UART2_BASE    (U8500_PER3_BASE + 0x7000)
0112 #define U8500_SDI5_BASE     (U8500_PER3_BASE + 0x8000)
0113 #define U8500_CLKRST3_BASE  (U8500_PER3_BASE + 0xf000)
0114
0115 /* per2 base addresses */
0116 #define U8500_I2C3_BASE     (U8500_PER2_BASE + 0x0000)
0117 #define U8500_SPI2_BASE     (U8500_PER2_BASE + 0x1000)
0118 #define U8500_SPI1_BASE     (U8500_PER2_BASE + 0x2000)
0119 #define U8500_PWL_BASE      (U8500_PER2_BASE + 0x3000)
0120 #define U8500_SDI4_BASE     (U8500_PER2_BASE + 0x4000)
0121 #define U8500_MSP2_BASE     (U8500_PER2_BASE + 0x7000)
0122 #define U8500_SDI1_BASE     (U8500_PER2_BASE + 0x8000)
0123 #define U8500_SDI3_BASE     (U8500_PER2_BASE + 0x9000)
0124 #define U8500_SPI0_BASE     (U8500_PER2_BASE + 0xa000)
0125 #define U8500_HSIR_BASE     (U8500_PER2_BASE + 0xb000)
0126 #define U8500_HSIT_BASE     (U8500_PER2_BASE + 0xc000)
0127 #define U8500_CLKRST2_BASE  (U8500_PER2_BASE + 0xf000)
0128
0129 /* per1 base addresses */
0130 #define U8500_I2C1_BASE     (U8500_PER1_BASE + 0x2000)
0131 #define U8500_MSP0_BASE     (U8500_PER1_BASE + 0x3000)
0132 #define U8500_MSP1_BASE     (U8500_PER1_BASE + 0x4000)
0133 #define U8500_MSP3_BASE     (U8500_PER1_BASE + 0x5000)
0134 #define U8500_SDI0_BASE     (U8500_PER1_BASE + 0x6000)
0135 #define U8500_I2C2_BASE     (U8500_PER1_BASE + 0x8000)
0136 #define U8500_SPI3_BASE     (U8500_PER1_BASE + 0x9000)
0137 #define U8500_I2C4_BASE     (U8500_PER1_BASE + 0xa000)
0138 #define U8500_SLIM0_BASE    (U8500_PER1_BASE + 0xb000)
0139 #define U8500_CLKRST1_BASE  (U8500_PER1_BASE + 0xf000)
0140
0141 #define U8500_SHRM_GOP_INTERRUPT_BASE   0xB7C00040
0142
0143 #define U8500_GPIOBANK0_BASE    U8500_GPIO0_BASE
0144 #define U8500_GPIOBANK1_BASE    (U8500_GPIO0_BASE + 0x80)
0145 #define U8500_GPIOBANK2_BASE    U8500_GPIO1_BASE
0146 #define U8500_GPIOBANK3_BASE    (U8500_GPIO1_BASE + 0x80)
0147 #define U8500_GPIOBANK4_BASE    (U8500_GPIO1_BASE + 0x100)
0148 #define U8500_GPIOBANK5_BASE    (U8500_GPIO1_BASE + 0x180)
0149 #define U8500_GPIOBANK6_BASE    U8500_GPIO2_BASE
0150 #define U8500_GPIOBANK7_BASE    (U8500_GPIO2_BASE + 0x80)
0151 #define U8500_GPIOBANK8_BASE    U8500_GPIO3_BASE
0152
0153 #define U8500_MCDE_SIZE     0x1000
0154 #define U8500_DSI_LINK_SIZE 0x1000
0155 #define U8500_DSI_LINK1_BASE    (U8500_MCDE_BASE + U8500_MCDE_SIZE)
0156 #define U8500_DSI_LINK2_BASE    (U8500_DSI_LINK1_BASE + U8500_DSI_LINK_SIZE)
0157 #define U8500_DSI_LINK3_BASE    (U8500_DSI_LINK2_BASE + U8500_DSI_LINK_SIZE)
0158 #define U8500_DSI_LINK_COUNT    0x3
0159
0160 /* Modem and APE physical addresses */
0161 #define U8500_MODEM_BASE    0xe000000
0162 #define U8500_APE_BASE      0x6000000
0163
0164 /* SoC identification number information */
0165 #define U8500_BB_UID_BASE      (U8500_BACKUPRAM1_BASE + 0xFC0)
0166
0167 /* Offsets to specific addresses in some IP blocks for DMA */
0168 #define MSP_TX_RX_REG_OFFSET    0
0169 #define CRYP1_RX_REG_OFFSET 0x10
0170 #define CRYP1_TX_REG_OFFSET 0x8
0171 #define HASH1_TX_REG_OFFSET 0x4
0172
0173 /*
0174  * Macros to get at IO space when running virtually
0175  * We dont map all the peripherals, let ioremap do
0176  * this for us. We map only very basic peripherals here.
0177  */
0178 #define U8500_IO_VIRTUAL    0xf0000000
0179 #define U8500_IO_PHYSICAL   0xa0000000
0180 /* This is where we map in the ROM to check ASIC IDs */
0181 #define UX500_VIRT_ROM      IOMEM(0xf0000000)
0182
0183 /* This macro is used in assembly, so no cast */
0184 #define IO_ADDRESS(x)           \
0185     (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + U8500_IO_VIRTUAL)
0186
0187 /* typesafe io address */
0188 #define __io_address(n)     IOMEM(IO_ADDRESS(n))
0189
0190 /* Used by some plat-nomadik code */
0191 #define io_p2v(n)       __io_address(n)
0192
0193 #define ARRAY_AND_SIZE(x)   (x), ARRAY_SIZE(x)
0194
0195 #endif