arm/mach-tegra/tegra.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * NVIDIA Tegra SoC device tree board support
0004  *
0005  * Copyright (C) 2011, 2013, NVIDIA Corporation
0006  * Copyright (C) 2010 Secret Lab Technologies, Ltd.
0007  * Copyright (C) 2010 Google, Inc.
0008  */
0009
0010 #include <linux/clk.h>
0011 #include <linux/clk/tegra.h>
0012 #include <linux/dma-mapping.h>
0013 #include <linux/init.h>
0014 #include <linux/io.h>
0015 #include <linux/irqchip.h>
0016 #include <linux/irqdomain.h>
0017 #include <linux/kernel.h>
0018 #include <linux/of_address.h>
0019 #include <linux/of_fdt.h>
0020 #include <linux/of.h>
0021 #include <linux/of_platform.h>
0022 #include <linux/pda_power.h>
0023 #include <linux/platform_device.h>
0024 #include <linux/serial_8250.h>
0025 #include <linux/slab.h>
0026 #include <linux/sys_soc.h>
0027 #include <linux/usb/tegra_usb_phy.h>
0028
0029 #include <linux/firmware/trusted_foundations.h>
0030
0031 #include <soc/tegra/fuse.h>
0032 #include <soc/tegra/pmc.h>
0033
0034 #include <asm/firmware.h>
0035 #include <asm/hardware/cache-l2x0.h>
0036 #include <asm/mach/arch.h>
0037 #include <asm/mach/time.h>
0038 #include <asm/mach-types.h>
0039 #include <asm/psci.h>
0040 #include <asm/setup.h>
0041
0042 #include "board.h"
0043 #include "common.h"
0044 #include "iomap.h"
0045 #include "pm.h"
0046 #include "reset.h"
0047 #include "sleep.h"
0048
0049 /*
0050  * Storage for debug-macro.S's state.
0051  *
0052  * This must be in .data not .bss so that it gets initialized each time the
0053  * kernel is loaded. The data is declared here rather than debug-macro.S so
0054  * that multiple inclusions of debug-macro.S point at the same data.
0055  */
0056 u32 tegra_uart_config[3] = {
0057     /* Debug UART initialization required */
0058     1,
0059     /* Debug UART physical address */
0060     0,
0061     /* Debug UART virtual address */
0062     0,
0063 };
0064
0065 static void __init tegra_init_early(void)
0066 {
0067     of_register_trusted_foundations();
0068     tegra_cpu_reset_handler_init();
0069     call_firmware_op(l2x0_init);
0070 }
0071
0072 static void __init tegra_dt_init_irq(void)
0073 {
0074     tegra_init_irq();
0075     irqchip_init();
0076 }
0077
0078 static void __init tegra_dt_init(void)
0079 {
0080     struct device *parent = tegra_soc_device_register();
0081
0082     of_platform_default_populate(NULL, NULL, parent);
0083 }
0084
0085 static void __init tegra_dt_init_late(void)
0086 {
0087     if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) &&
0088         of_machine_is_compatible("compal,paz00"))
0089         tegra_paz00_wifikill_init();
0090
0091     if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) &&
0092         of_machine_is_compatible("nvidia,tegra20"))
0093         platform_device_register_simple("tegra20-cpufreq", -1, NULL, 0);
0094
0095     if (IS_ENABLED(CONFIG_ARM_TEGRA_CPUIDLE) && !psci_smp_available())
0096         platform_device_register_simple("tegra-cpuidle", -1, NULL, 0);
0097
0098     if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) &&
0099         of_machine_is_compatible("nvidia,tegra30"))
0100         platform_device_register_simple("tegra20-cpufreq", -1, NULL, 0);
0101 }
0102
0103 static const char * const tegra_dt_board_compat[] = {
0104     "nvidia,tegra124",
0105     "nvidia,tegra114",
0106     "nvidia,tegra30",
0107     "nvidia,tegra20",
0108     NULL
0109 };
0110
0111 DT_MACHINE_START(TEGRA_DT, "NVIDIA Tegra SoC (Flattened Device Tree)")
0112     .l2c_aux_val    = 0x3c400000,
0113     .l2c_aux_mask   = 0xc20fc3ff,
0114     .smp        = smp_ops(tegra_smp_ops),
0115     .map_io     = tegra_map_common_io,
0116     .init_early = tegra_init_early,
0117     .init_irq   = tegra_dt_init_irq,
0118     .init_machine   = tegra_dt_init,
0119     .init_late  = tegra_dt_init_late,
0120     .dt_compat  = tegra_dt_board_compat,
0121 MACHINE_END