arm/mach-tegra/sleep.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (c) 2010-2013, NVIDIA Corporation. All rights reserved.
0004  */
0005
0006 #ifndef __MACH_TEGRA_SLEEP_H
0007 #define __MACH_TEGRA_SLEEP_H
0008
0009 #include "iomap.h"
0010 #include "irammap.h"
0011
0012 #define TEGRA_ARM_PERIF_VIRT (TEGRA_ARM_PERIF_BASE - IO_CPU_PHYS \
0013                     + IO_CPU_VIRT)
0014 #define TEGRA_FLOW_CTRL_VIRT (TEGRA_FLOW_CTRL_BASE - IO_PPSB_PHYS \
0015                     + IO_PPSB_VIRT)
0016 #define TEGRA_CLK_RESET_VIRT (TEGRA_CLK_RESET_BASE - IO_PPSB_PHYS \
0017                     + IO_PPSB_VIRT)
0018 #define TEGRA_APB_MISC_VIRT (TEGRA_APB_MISC_BASE - IO_APB_PHYS \
0019                     + IO_APB_VIRT)
0020 #define TEGRA_PMC_VIRT  (TEGRA_PMC_BASE - IO_APB_PHYS + IO_APB_VIRT)
0021
0022 #define TEGRA_IRAM_RESET_BASE_VIRT (IO_IRAM_VIRT + \
0023                 TEGRA_IRAM_RESET_HANDLER_OFFSET)
0024
0025 /* PMC_SCRATCH37-39 and 41 are used for tegra_pen_lock and idle */
0026 #define PMC_SCRATCH37   0x130
0027 #define PMC_SCRATCH38   0x134
0028 #define PMC_SCRATCH39   0x138
0029 #define PMC_SCRATCH41   0x140
0030
0031 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
0032 #define CPU_RESETTABLE      2
0033 #define CPU_RESETTABLE_SOON 1
0034 #define CPU_NOT_RESETTABLE  0
0035 #endif
0036
0037 /* flag of tegra_disable_clean_inv_dcache to do LoUIS or all */
0038 #define TEGRA_FLUSH_CACHE_LOUIS 0
0039 #define TEGRA_FLUSH_CACHE_ALL   1
0040
0041 #ifdef __ASSEMBLY__
0042 /* waits until the microsecond counter (base) is > rn */
0043 .macro wait_until, rn, base, tmp
0044     add \rn, \rn, #1
0045 1001:   ldr \tmp, [\base]
0046     cmp \tmp, \rn
0047     bmi 1001b
0048 .endm
0049
0050 /* returns the offset of the flow controller halt register for a cpu */
0051 .macro cpu_to_halt_reg rd, rcpu
0052     cmp \rcpu, #0
0053     subne   \rd, \rcpu, #1
0054     movne   \rd, \rd, lsl #3
0055     addne   \rd, \rd, #0x14
0056     moveq   \rd, #0
0057 .endm
0058
0059 /* returns the offset of the flow controller csr register for a cpu */
0060 .macro cpu_to_csr_reg rd, rcpu
0061     cmp \rcpu, #0
0062     subne   \rd, \rcpu, #1
0063     movne   \rd, \rd, lsl #3
0064     addne   \rd, \rd, #0x18
0065     moveq   \rd, #8
0066 .endm
0067
0068 /* returns the ID of the current processor */
0069 .macro cpu_id, rd
0070     mrc p15, 0, \rd, c0, c0, 5
0071     and \rd, \rd, #0xF
0072 .endm
0073
0074 /* loads a 32-bit value into a register without a data access */
0075 .macro mov32, reg, val
0076     movw    \reg, #:lower16:\val
0077     movt    \reg, #:upper16:\val
0078 .endm
0079
0080 /* Marco to check CPU part num */
0081 .macro check_cpu_part_num part_num, tmp1, tmp2
0082     mrc p15, 0, \tmp1, c0, c0, 0
0083     ubfx    \tmp1, \tmp1, #4, #12
0084     mov32   \tmp2, \part_num
0085     cmp \tmp1, \tmp2
0086 .endm
0087
0088 /* Macro to exit SMP coherency. */
0089 .macro exit_smp, tmp1, tmp2
0090     mrc p15, 0, \tmp1, c1, c0, 1    @ ACTLR
0091     bic \tmp1, \tmp1, #(1<<6) | (1<<0)  @ clear ACTLR.SMP | ACTLR.FW
0092     mcr p15, 0, \tmp1, c1, c0, 1    @ ACTLR
0093     isb
0094 #ifdef CONFIG_HAVE_ARM_SCU
0095     check_cpu_part_num 0xc09, \tmp1, \tmp2
0096     mrceq   p15, 0, \tmp1, c0, c0, 5
0097     andeq   \tmp1, \tmp1, #0xF
0098     moveq   \tmp1, \tmp1, lsl #2
0099     moveq   \tmp2, #0xf
0100     moveq   \tmp2, \tmp2, lsl \tmp1
0101     ldreq   \tmp1, =(TEGRA_ARM_PERIF_VIRT + 0xC)
0102     streq   \tmp2, [\tmp1]          @ invalidate SCU tags for CPU
0103     dsb
0104 #endif
0105 .endm
0106
0107 /* Macro to check Tegra revision */
0108 #define APB_MISC_GP_HIDREV  0x804
0109 .macro tegra_get_soc_id base, tmp1
0110     mov32   \tmp1, \base
0111     ldr \tmp1, [\tmp1, #APB_MISC_GP_HIDREV]
0112     and \tmp1, \tmp1, #0xff00
0113     mov \tmp1, \tmp1, lsr #8
0114 .endm
0115
0116 #else
0117 void tegra_resume(void);
0118 int tegra_sleep_cpu_finish(unsigned long);
0119 void tegra_disable_clean_inv_dcache(u32 flag);
0120
0121 void tegra20_hotplug_shutdown(void);
0122 void tegra30_hotplug_shutdown(void);
0123
0124 void tegra20_tear_down_cpu(void);
0125 void tegra30_tear_down_cpu(void);
0126
0127 #endif
0128 #endif