arm/mach-tegra/reset.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * arch/arm/mach-tegra/reset.h
0004  *
0005  * CPU reset dispatcher.
0006  *
0007  * Copyright (c) 2011, NVIDIA Corporation.
0008  */
0009
0010 #ifndef __MACH_TEGRA_RESET_H
0011 #define __MACH_TEGRA_RESET_H
0012
0013 #define TEGRA_RESET_MASK_PRESENT    0
0014 #define TEGRA_RESET_MASK_LP1        1
0015 #define TEGRA_RESET_MASK_LP2        2
0016 #define TEGRA_RESET_STARTUP_SECONDARY   3
0017 #define TEGRA_RESET_STARTUP_LP2     4
0018 #define TEGRA_RESET_STARTUP_LP1     5
0019 #define TEGRA_RESET_TF_PRESENT      6
0020 #define TEGRA_RESET_DATA_SIZE       7
0021
0022 #define RESET_DATA(x)   ((TEGRA_RESET_##x)*4)
0023
0024 #ifndef __ASSEMBLY__
0025
0026 #include "irammap.h"
0027
0028 extern unsigned long __tegra_cpu_reset_handler_data[TEGRA_RESET_DATA_SIZE];
0029
0030 void __tegra_cpu_reset_handler_start(void);
0031 void __tegra_cpu_reset_handler(void);
0032 void __tegra20_cpu1_resettable_status_offset(void);
0033 void __tegra_cpu_reset_handler_end(void);
0034
0035 #ifdef CONFIG_PM_SLEEP
0036 #define tegra_cpu_lp1_mask \
0037     (IO_ADDRESS(TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET + \
0038     ((u32)&__tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_LP1] - \
0039      (u32)__tegra_cpu_reset_handler_start)))
0040 #define tegra_cpu_lp2_mask \
0041     (IO_ADDRESS(TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET + \
0042     ((u32)&__tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_LP2] - \
0043      (u32)__tegra_cpu_reset_handler_start)))
0044 #endif
0045
0046 #define tegra_cpu_reset_handler_offset \
0047         ((u32)__tegra_cpu_reset_handler - \
0048          (u32)__tegra_cpu_reset_handler_start)
0049
0050 #define tegra_cpu_reset_handler_size \
0051         (__tegra_cpu_reset_handler_end - \
0052          __tegra_cpu_reset_handler_start)
0053
0054 void __init tegra_cpu_reset_handler_init(void);
0055
0056 #endif
0057 #endif