arm/mach-tegra/pm.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * CPU complex suspend & resume functions for Tegra SoCs
0004  *
0005  * Copyright (c) 2009-2012, NVIDIA Corporation. All rights reserved.
0006  */
0007
0008 #include <linux/clk/tegra.h>
0009 #include <linux/cpumask.h>
0010 #include <linux/cpu_pm.h>
0011 #include <linux/delay.h>
0012 #include <linux/err.h>
0013 #include <linux/io.h>
0014 #include <linux/kernel.h>
0015 #include <linux/slab.h>
0016 #include <linux/spinlock.h>
0017 #include <linux/suspend.h>
0018
0019 #include <linux/firmware/trusted_foundations.h>
0020
0021 #include <soc/tegra/flowctrl.h>
0022 #include <soc/tegra/fuse.h>
0023 #include <soc/tegra/pm.h>
0024 #include <soc/tegra/pmc.h>
0025
0026 #include <asm/cacheflush.h>
0027 #include <asm/firmware.h>
0028 #include <asm/idmap.h>
0029 #include <asm/proc-fns.h>
0030 #include <asm/smp_plat.h>
0031 #include <asm/suspend.h>
0032 #include <asm/tlbflush.h>
0033
0034 #include "iomap.h"
0035 #include "pm.h"
0036 #include "reset.h"
0037 #include "sleep.h"
0038
0039 #ifdef CONFIG_PM_SLEEP
0040 static DEFINE_SPINLOCK(tegra_lp2_lock);
0041 static u32 iram_save_size;
0042 static void *iram_save_addr;
0043 struct tegra_lp1_iram tegra_lp1_iram;
0044 void (*tegra_tear_down_cpu)(void);
0045 void (*tegra_sleep_core_finish)(unsigned long v2p);
0046 static int (*tegra_sleep_func)(unsigned long v2p);
0047
0048 static void tegra_tear_down_cpu_init(void)
0049 {
0050     switch (tegra_get_chip_id()) {
0051     case TEGRA20:
0052         if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC))
0053             tegra_tear_down_cpu = tegra20_tear_down_cpu;
0054         break;
0055     case TEGRA30:
0056     case TEGRA114:
0057     case TEGRA124:
0058         if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) ||
0059             IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) ||
0060             IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC))
0061             tegra_tear_down_cpu = tegra30_tear_down_cpu;
0062         break;
0063     }
0064 }
0065
0066 /*
0067  * restore_cpu_complex
0068  *
0069  * restores cpu clock setting, clears flow controller
0070  *
0071  * Always called on CPU 0.
0072  */
0073 static void restore_cpu_complex(void)
0074 {
0075     int cpu = smp_processor_id();
0076
0077     BUG_ON(cpu != 0);
0078
0079 #ifdef CONFIG_SMP
0080     cpu = cpu_logical_map(cpu);
0081 #endif
0082
0083     /* Restore the CPU clock settings */
0084     tegra_cpu_clock_resume();
0085
0086     flowctrl_cpu_suspend_exit(cpu);
0087 }
0088
0089 /*
0090  * suspend_cpu_complex
0091  *
0092  * saves pll state for use by restart_plls, prepares flow controller for
0093  * transition to suspend state
0094  *
0095  * Must always be called on cpu 0.
0096  */
0097 static void suspend_cpu_complex(void)
0098 {
0099     int cpu = smp_processor_id();
0100
0101     BUG_ON(cpu != 0);
0102
0103 #ifdef CONFIG_SMP
0104     cpu = cpu_logical_map(cpu);
0105 #endif
0106
0107     /* Save the CPU clock settings */
0108     tegra_cpu_clock_suspend();
0109
0110     flowctrl_cpu_suspend_enter(cpu);
0111 }
0112
0113 void tegra_pm_clear_cpu_in_lp2(void)
0114 {
0115     int phy_cpu_id = cpu_logical_map(smp_processor_id());
0116     u32 *cpu_in_lp2 = tegra_cpu_lp2_mask;
0117
0118     spin_lock(&tegra_lp2_lock);
0119
0120     BUG_ON(!(*cpu_in_lp2 & BIT(phy_cpu_id)));
0121     *cpu_in_lp2 &= ~BIT(phy_cpu_id);
0122
0123     spin_unlock(&tegra_lp2_lock);
0124 }
0125
0126 void tegra_pm_set_cpu_in_lp2(void)
0127 {
0128     int phy_cpu_id = cpu_logical_map(smp_processor_id());
0129     u32 *cpu_in_lp2 = tegra_cpu_lp2_mask;
0130
0131     spin_lock(&tegra_lp2_lock);
0132
0133     BUG_ON((*cpu_in_lp2 & BIT(phy_cpu_id)));
0134     *cpu_in_lp2 |= BIT(phy_cpu_id);
0135
0136     spin_unlock(&tegra_lp2_lock);
0137 }
0138
0139 static int tegra_sleep_cpu(unsigned long v2p)
0140 {
0141     if (tegra_cpu_car_ops->rail_off_ready &&
0142         WARN_ON(!tegra_cpu_rail_off_ready()))
0143         return -EBUSY;
0144
0145     /*
0146      * L2 cache disabling using kernel API only allowed when all
0147      * secondary CPU's are offline. Cache have to be disabled with
0148      * MMU-on if cache maintenance is done via Trusted Foundations
0149      * firmware. Note that CPUIDLE won't ever enter powergate on Tegra30
0150      * if any of secondary CPU's is online and this is the LP2-idle
0151      * code-path only for Tegra20/30.
0152      */
0153 #ifdef CONFIG_OUTER_CACHE
0154     if (trusted_foundations_registered() && outer_cache.disable)
0155         outer_cache.disable();
0156 #endif
0157     /*
0158      * Note that besides of setting up CPU reset vector this firmware
0159      * call may also do the following, depending on the FW version:
0160      *  1) Disable L2. But this doesn't matter since we already
0161      *     disabled the L2.
0162      *  2) Disable D-cache. This need to be taken into account in
0163      *     particular by the tegra_disable_clean_inv_dcache() which
0164      *     shall avoid the re-disable.
0165      */
0166     call_firmware_op(prepare_idle, TF_PM_MODE_LP2);
0167
0168     setup_mm_for_reboot();
0169     tegra_sleep_cpu_finish(v2p);
0170
0171     /* should never here */
0172     BUG();
0173
0174     return 0;
0175 }
0176
0177 static void tegra_pm_set(enum tegra_suspend_mode mode)
0178 {
0179     u32 value;
0180
0181     switch (tegra_get_chip_id()) {
0182     case TEGRA20:
0183     case TEGRA30:
0184         break;
0185     default:
0186         /* Turn off CRAIL */
0187         value = flowctrl_read_cpu_csr(0);
0188         value &= ~FLOW_CTRL_CSR_ENABLE_EXT_MASK;
0189         value |= FLOW_CTRL_CSR_ENABLE_EXT_CRAIL;
0190         flowctrl_write_cpu_csr(0, value);
0191         break;
0192     }
0193
0194     tegra_pmc_enter_suspend_mode(mode);
0195 }
0196
0197 int tegra_pm_enter_lp2(void)
0198 {
0199     int err;
0200
0201     tegra_pm_set(TEGRA_SUSPEND_LP2);
0202
0203     cpu_cluster_pm_enter();
0204     suspend_cpu_complex();
0205
0206     err = cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, &tegra_sleep_cpu);
0207
0208     /*
0209      * Resume L2 cache if it wasn't re-enabled early during resume,
0210      * which is the case for Tegra30 that has to re-enable the cache
0211      * via firmware call. In other cases cache is already enabled and
0212      * hence re-enabling is a no-op. This is always a no-op on Tegra114+.
0213      */
0214     outer_resume();
0215
0216     restore_cpu_complex();
0217     cpu_cluster_pm_exit();
0218
0219     call_firmware_op(prepare_idle, TF_PM_MODE_NONE);
0220
0221     return err;
0222 }
0223
0224 enum tegra_suspend_mode tegra_pm_validate_suspend_mode(
0225                 enum tegra_suspend_mode mode)
0226 {
0227     /*
0228      * The Tegra devices support suspending to LP1 or lower currently.
0229      */
0230     if (mode > TEGRA_SUSPEND_LP1)
0231         return TEGRA_SUSPEND_LP1;
0232
0233     return mode;
0234 }
0235
0236 static int tegra_sleep_core(unsigned long v2p)
0237 {
0238     /*
0239      * Cache have to be disabled with MMU-on if cache maintenance is done
0240      * via Trusted Foundations firmware. This is a no-op on Tegra114+.
0241      */
0242     if (trusted_foundations_registered())
0243         outer_disable();
0244
0245     call_firmware_op(prepare_idle, TF_PM_MODE_LP1);
0246
0247     setup_mm_for_reboot();
0248     tegra_sleep_core_finish(v2p);
0249
0250     /* should never here */
0251     BUG();
0252
0253     return 0;
0254 }
0255
0256 /*
0257  * tegra_lp1_iram_hook
0258  *
0259  * Hooking the address of LP1 reset vector and SDRAM self-refresh code in
0260  * SDRAM. These codes not be copied to IRAM in this fuction. We need to
0261  * copy these code to IRAM before LP0/LP1 suspend and restore the content
0262  * of IRAM after resume.
0263  */
0264 static bool tegra_lp1_iram_hook(void)
0265 {
0266     switch (tegra_get_chip_id()) {
0267     case TEGRA20:
0268         if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC))
0269             tegra20_lp1_iram_hook();
0270         break;
0271     case TEGRA30:
0272     case TEGRA114:
0273     case TEGRA124:
0274         if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) ||
0275             IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) ||
0276             IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC))
0277             tegra30_lp1_iram_hook();
0278         break;
0279     default:
0280         break;
0281     }
0282
0283     if (!tegra_lp1_iram.start_addr || !tegra_lp1_iram.end_addr)
0284         return false;
0285
0286     iram_save_size = tegra_lp1_iram.end_addr - tegra_lp1_iram.start_addr;
0287     iram_save_addr = kmalloc(iram_save_size, GFP_KERNEL);
0288     if (!iram_save_addr)
0289         return false;
0290
0291     return true;
0292 }
0293
0294 static bool tegra_sleep_core_init(void)
0295 {
0296     switch (tegra_get_chip_id()) {
0297     case TEGRA20:
0298         if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC))
0299             tegra20_sleep_core_init();
0300         break;
0301     case TEGRA30:
0302     case TEGRA114:
0303     case TEGRA124:
0304         if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) ||
0305             IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) ||
0306             IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC))
0307             tegra30_sleep_core_init();
0308         break;
0309     default:
0310         break;
0311     }
0312
0313     if (!tegra_sleep_core_finish)
0314         return false;
0315
0316     return true;
0317 }
0318
0319 static void tegra_suspend_enter_lp1(void)
0320 {
0321     /* copy the reset vector & SDRAM shutdown code into IRAM */
0322     memcpy(iram_save_addr, IO_ADDRESS(TEGRA_IRAM_LPx_RESUME_AREA),
0323         iram_save_size);
0324     memcpy(IO_ADDRESS(TEGRA_IRAM_LPx_RESUME_AREA),
0325         tegra_lp1_iram.start_addr, iram_save_size);
0326
0327     *((u32 *)tegra_cpu_lp1_mask) = 1;
0328 }
0329
0330 static void tegra_suspend_exit_lp1(void)
0331 {
0332     /* restore IRAM */
0333     memcpy(IO_ADDRESS(TEGRA_IRAM_LPx_RESUME_AREA), iram_save_addr,
0334         iram_save_size);
0335
0336     *(u32 *)tegra_cpu_lp1_mask = 0;
0337 }
0338
0339 static const char *lp_state[TEGRA_MAX_SUSPEND_MODE] = {
0340     [TEGRA_SUSPEND_NONE] = "none",
0341     [TEGRA_SUSPEND_LP2] = "LP2",
0342     [TEGRA_SUSPEND_LP1] = "LP1",
0343     [TEGRA_SUSPEND_LP0] = "LP0",
0344 };
0345
0346 static int tegra_suspend_enter(suspend_state_t state)
0347 {
0348     enum tegra_suspend_mode mode = tegra_pmc_get_suspend_mode();
0349
0350     if (WARN_ON(mode < TEGRA_SUSPEND_NONE ||
0351             mode >= TEGRA_MAX_SUSPEND_MODE))
0352         return -EINVAL;
0353
0354     pr_info("Entering suspend state %s\n", lp_state[mode]);
0355
0356     tegra_pm_set(mode);
0357
0358     local_fiq_disable();
0359
0360     suspend_cpu_complex();
0361     switch (mode) {
0362     case TEGRA_SUSPEND_LP1:
0363         tegra_suspend_enter_lp1();
0364         break;
0365     case TEGRA_SUSPEND_LP2:
0366         tegra_pm_set_cpu_in_lp2();
0367         break;
0368     default:
0369         break;
0370     }
0371
0372     cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, tegra_sleep_func);
0373
0374     /*
0375      * Resume L2 cache if it wasn't re-enabled early during resume,
0376      * which is the case for Tegra30 that has to re-enable the cache
0377      * via firmware call. In other cases cache is already enabled and
0378      * hence re-enabling is a no-op.
0379      */
0380     outer_resume();
0381
0382     switch (mode) {
0383     case TEGRA_SUSPEND_LP1:
0384         tegra_suspend_exit_lp1();
0385         break;
0386     case TEGRA_SUSPEND_LP2:
0387         tegra_pm_clear_cpu_in_lp2();
0388         break;
0389     default:
0390         break;
0391     }
0392     restore_cpu_complex();
0393
0394     local_fiq_enable();
0395
0396     call_firmware_op(prepare_idle, TF_PM_MODE_NONE);
0397
0398     return 0;
0399 }
0400
0401 static const struct platform_suspend_ops tegra_suspend_ops = {
0402     .valid      = suspend_valid_only_mem,
0403     .enter      = tegra_suspend_enter,
0404 };
0405
0406 void tegra_pm_init_suspend(void)
0407 {
0408     enum tegra_suspend_mode mode = tegra_pmc_get_suspend_mode();
0409
0410     if (mode == TEGRA_SUSPEND_NONE)
0411         return;
0412
0413     tegra_tear_down_cpu_init();
0414
0415     if (mode >= TEGRA_SUSPEND_LP1) {
0416         if (!tegra_lp1_iram_hook() || !tegra_sleep_core_init()) {
0417             pr_err("%s: unable to allocate memory for SDRAM"
0418                    "self-refresh -- LP0/LP1 unavailable\n",
0419                    __func__);
0420             tegra_pmc_set_suspend_mode(TEGRA_SUSPEND_LP2);
0421             mode = TEGRA_SUSPEND_LP2;
0422         }
0423     }
0424
0425     /* set up sleep function for cpu_suspend */
0426     switch (mode) {
0427     case TEGRA_SUSPEND_LP1:
0428         tegra_sleep_func = tegra_sleep_core;
0429         break;
0430     case TEGRA_SUSPEND_LP2:
0431         tegra_sleep_func = tegra_sleep_cpu;
0432         break;
0433     default:
0434         break;
0435     }
0436
0437     suspend_set_ops(&tegra_suspend_ops);
0438 }
0439
0440 int tegra_pm_park_secondary_cpu(unsigned long cpu)
0441 {
0442     if (cpu > 0) {
0443         tegra_disable_clean_inv_dcache(TEGRA_FLUSH_CACHE_LOUIS);
0444
0445         if (tegra_get_chip_id() == TEGRA20)
0446             tegra20_hotplug_shutdown();
0447         else
0448             tegra30_hotplug_shutdown();
0449     }
0450
0451     return -EINVAL;
0452 }
0453 #endif