arm/mach-tegra/platsmp.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  *  linux/arch/arm/mach-tegra/platsmp.c
0004  *
0005  *  Copyright (C) 2002 ARM Ltd.
0006  *  All Rights Reserved
0007  *
0008  *  Copyright (C) 2009 Palm
0009  *  All Rights Reserved
0010  */
0011
0012 #include <linux/clk/tegra.h>
0013 #include <linux/delay.h>
0014 #include <linux/device.h>
0015 #include <linux/errno.h>
0016 #include <linux/init.h>
0017 #include <linux/io.h>
0018 #include <linux/jiffies.h>
0019 #include <linux/smp.h>
0020
0021 #include <soc/tegra/flowctrl.h>
0022 #include <soc/tegra/fuse.h>
0023 #include <soc/tegra/pmc.h>
0024
0025 #include <asm/cacheflush.h>
0026 #include <asm/mach-types.h>
0027 #include <asm/smp_plat.h>
0028 #include <asm/smp_scu.h>
0029
0030 #include "common.h"
0031 #include "iomap.h"
0032 #include "reset.h"
0033
0034 static cpumask_t tegra_cpu_init_mask;
0035
0036 static void tegra_secondary_init(unsigned int cpu)
0037 {
0038     cpumask_set_cpu(cpu, &tegra_cpu_init_mask);
0039 }
0040
0041
0042 static int tegra20_boot_secondary(unsigned int cpu, struct task_struct *idle)
0043 {
0044     cpu = cpu_logical_map(cpu);
0045
0046     /*
0047      * Force the CPU into reset. The CPU must remain in reset when
0048      * the flow controller state is cleared (which will cause the
0049      * flow controller to stop driving reset if the CPU has been
0050      * power-gated via the flow controller). This will have no
0051      * effect on first boot of the CPU since it should already be
0052      * in reset.
0053      */
0054     tegra_put_cpu_in_reset(cpu);
0055
0056     /*
0057      * Unhalt the CPU. If the flow controller was used to
0058      * power-gate the CPU this will cause the flow controller to
0059      * stop driving reset. The CPU will remain in reset because the
0060      * clock and reset block is now driving reset.
0061      */
0062     flowctrl_write_cpu_halt(cpu, 0);
0063
0064     tegra_enable_cpu_clock(cpu);
0065     flowctrl_write_cpu_csr(cpu, 0); /* Clear flow controller CSR. */
0066     tegra_cpu_out_of_reset(cpu);
0067     return 0;
0068 }
0069
0070 static int tegra30_boot_secondary(unsigned int cpu, struct task_struct *idle)
0071 {
0072     int ret;
0073     unsigned long timeout;
0074
0075     cpu = cpu_logical_map(cpu);
0076     tegra_put_cpu_in_reset(cpu);
0077     flowctrl_write_cpu_halt(cpu, 0);
0078
0079     /*
0080      * The power up sequence of cold boot CPU and warm boot CPU
0081      * was different.
0082      *
0083      * For warm boot CPU that was resumed from CPU hotplug, the
0084      * power will be resumed automatically after un-halting the
0085      * flow controller of the warm boot CPU. We need to wait for
0086      * the confirmation that the CPU is powered then removing
0087      * the IO clamps.
0088      * For cold boot CPU, do not wait. After the cold boot CPU be
0089      * booted, it will run to tegra_secondary_init() and set
0090      * tegra_cpu_init_mask which influences what tegra30_boot_secondary()
0091      * next time around.
0092      */
0093     if (cpumask_test_cpu(cpu, &tegra_cpu_init_mask)) {
0094         timeout = jiffies + msecs_to_jiffies(50);
0095         do {
0096             if (tegra_pmc_cpu_is_powered(cpu))
0097                 goto remove_clamps;
0098             udelay(10);
0099         } while (time_before(jiffies, timeout));
0100     }
0101
0102     /*
0103      * The power status of the cold boot CPU is power gated as
0104      * default. To power up the cold boot CPU, the power should
0105      * be un-gated by un-toggling the power gate register
0106      * manually.
0107      */
0108     ret = tegra_pmc_cpu_power_on(cpu);
0109     if (ret)
0110         return ret;
0111
0112 remove_clamps:
0113     /* CPU partition is powered. Enable the CPU clock. */
0114     tegra_enable_cpu_clock(cpu);
0115     udelay(10);
0116
0117     /* Remove I/O clamps. */
0118     ret = tegra_pmc_cpu_remove_clamping(cpu);
0119     if (ret)
0120         return ret;
0121
0122     udelay(10);
0123
0124     flowctrl_write_cpu_csr(cpu, 0); /* Clear flow controller CSR. */
0125     tegra_cpu_out_of_reset(cpu);
0126     return 0;
0127 }
0128
0129 static int tegra114_boot_secondary(unsigned int cpu, struct task_struct *idle)
0130 {
0131     int ret = 0;
0132
0133     cpu = cpu_logical_map(cpu);
0134
0135     if (cpumask_test_cpu(cpu, &tegra_cpu_init_mask)) {
0136         /*
0137          * Warm boot flow
0138          * The flow controller in charge of the power state and
0139          * control for each CPU.
0140          */
0141         /* set SCLK as event trigger for flow controller */
0142         flowctrl_write_cpu_csr(cpu, 1);
0143         flowctrl_write_cpu_halt(cpu,
0144                 FLOW_CTRL_WAITEVENT | FLOW_CTRL_SCLK_RESUME);
0145     } else {
0146         /*
0147          * Cold boot flow
0148          * The CPU is powered up by toggling PMC directly. It will
0149          * also initial power state in flow controller. After that,
0150          * the CPU's power state is maintained by flow controller.
0151          */
0152         ret = tegra_pmc_cpu_power_on(cpu);
0153     }
0154
0155     return ret;
0156 }
0157
0158 static int tegra_boot_secondary(unsigned int cpu,
0159                       struct task_struct *idle)
0160 {
0161     if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) && tegra_get_chip_id() == TEGRA20)
0162         return tegra20_boot_secondary(cpu, idle);
0163     if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) && tegra_get_chip_id() == TEGRA30)
0164         return tegra30_boot_secondary(cpu, idle);
0165     if (IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) && tegra_get_chip_id() == TEGRA114)
0166         return tegra114_boot_secondary(cpu, idle);
0167     if (IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC) && tegra_get_chip_id() == TEGRA124)
0168         return tegra114_boot_secondary(cpu, idle);
0169
0170     return -EINVAL;
0171 }
0172
0173 static void __init tegra_smp_prepare_cpus(unsigned int max_cpus)
0174 {
0175     /* Always mark the boot CPU (CPU0) as initialized. */
0176     cpumask_set_cpu(0, &tegra_cpu_init_mask);
0177
0178     if (scu_a9_has_base())
0179         scu_enable(IO_ADDRESS(scu_a9_get_base()));
0180 }
0181
0182 const struct smp_operations tegra_smp_ops __initconst = {
0183     .smp_prepare_cpus   = tegra_smp_prepare_cpus,
0184     .smp_secondary_init = tegra_secondary_init,
0185     .smp_boot_secondary = tegra_boot_secondary,
0186 #ifdef CONFIG_HOTPLUG_CPU
0187     .cpu_kill       = tegra_cpu_kill,
0188     .cpu_die        = tegra_cpu_die,
0189 #endif
0190 };