arm/mach-tegra/iomap.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (C) 2010 Google, Inc.
0004  *
0005  * Author:
0006  *  Colin Cross <ccross@google.com>
0007  *  Erik Gilling <konkers@google.com>
0008  */
0009
0010 #ifndef __MACH_TEGRA_IOMAP_H
0011 #define __MACH_TEGRA_IOMAP_H
0012
0013 #include <linux/pgtable.h>
0014 #include <linux/sizes.h>
0015
0016 #define TEGRA_IRAM_BASE         0x40000000
0017 #define TEGRA_IRAM_SIZE         SZ_256K
0018
0019 #define TEGRA_ARM_PERIF_BASE        0x50040000
0020 #define TEGRA_ARM_PERIF_SIZE        SZ_8K
0021
0022 #define TEGRA_ARM_INT_DIST_BASE     0x50041000
0023 #define TEGRA_ARM_INT_DIST_SIZE     SZ_4K
0024
0025 #define TEGRA_TMR1_BASE         0x60005000
0026 #define TEGRA_TMR1_SIZE         SZ_8
0027
0028 #define TEGRA_TMR2_BASE         0x60005008
0029 #define TEGRA_TMR2_SIZE         SZ_8
0030
0031 #define TEGRA_TMRUS_BASE        0x60005010
0032 #define TEGRA_TMRUS_SIZE        SZ_64
0033
0034 #define TEGRA_TMR3_BASE         0x60005050
0035 #define TEGRA_TMR3_SIZE         SZ_8
0036
0037 #define TEGRA_TMR4_BASE         0x60005058
0038 #define TEGRA_TMR4_SIZE         SZ_8
0039
0040 #define TEGRA_CLK_RESET_BASE        0x60006000
0041 #define TEGRA_CLK_RESET_SIZE        SZ_4K
0042
0043 #define TEGRA_FLOW_CTRL_BASE        0x60007000
0044 #define TEGRA_FLOW_CTRL_SIZE        20
0045
0046 #define TEGRA_SB_BASE           0x6000C200
0047 #define TEGRA_SB_SIZE           256
0048
0049 #define TEGRA_EXCEPTION_VECTORS_BASE    0x6000F000
0050 #define TEGRA_EXCEPTION_VECTORS_SIZE    SZ_4K
0051
0052 #define TEGRA_APB_MISC_BASE     0x70000000
0053 #define TEGRA_APB_MISC_SIZE     SZ_4K
0054
0055 #define TEGRA_UARTA_BASE        0x70006000
0056 #define TEGRA_UARTA_SIZE        SZ_64
0057
0058 #define TEGRA_UARTB_BASE        0x70006040
0059 #define TEGRA_UARTB_SIZE        SZ_64
0060
0061 #define TEGRA_UARTC_BASE        0x70006200
0062 #define TEGRA_UARTC_SIZE        SZ_256
0063
0064 #define TEGRA_UARTD_BASE        0x70006300
0065 #define TEGRA_UARTD_SIZE        SZ_256
0066
0067 #define TEGRA_UARTE_BASE        0x70006400
0068 #define TEGRA_UARTE_SIZE        SZ_256
0069
0070 #define TEGRA_PMC_BASE          0x7000E400
0071 #define TEGRA_PMC_SIZE          SZ_256
0072
0073 #define TEGRA_EMC_BASE          0x7000F400
0074 #define TEGRA_EMC_SIZE          SZ_1K
0075
0076 #define TEGRA_EMC0_BASE         0x7001A000
0077 #define TEGRA_EMC0_SIZE         SZ_2K
0078
0079 #define TEGRA_EMC1_BASE         0x7001A800
0080 #define TEGRA_EMC1_SIZE         SZ_2K
0081
0082 #define TEGRA124_EMC_BASE       0x7001B000
0083 #define TEGRA124_EMC_SIZE       SZ_2K
0084
0085 #define TEGRA_CSITE_BASE        0x70040000
0086 #define TEGRA_CSITE_SIZE        SZ_256K
0087
0088 /* On TEGRA, many peripherals are very closely packed in
0089  * two 256MB io windows (that actually only use about 64KB
0090  * at the start of each).
0091  *
0092  * We will just map the first MMU section of each window (to minimize
0093  * pt entries needed) and provide a macro to transform physical
0094  * io addresses to an appropriate void __iomem *.
0095  */
0096
0097 #define IO_IRAM_PHYS    0x40000000
0098 #define IO_IRAM_VIRT    IOMEM(0xFE400000)
0099 #define IO_IRAM_SIZE    SZ_256K
0100
0101 #define IO_CPU_PHYS 0x50040000
0102 #define IO_CPU_VIRT IOMEM(0xFE440000)
0103 #define IO_CPU_SIZE SZ_16K
0104
0105 #define IO_PPSB_PHYS    0x60000000
0106 #define IO_PPSB_VIRT    IOMEM(0xFE200000)
0107 #define IO_PPSB_SIZE    SECTION_SIZE
0108
0109 #define IO_APB_PHYS 0x70000000
0110 #define IO_APB_VIRT IOMEM(0xFE000000)
0111 #define IO_APB_SIZE SECTION_SIZE
0112
0113 #define IO_TO_VIRT_BETWEEN(p, st, sz)   ((p) >= (st) && (p) < ((st) + (sz)))
0114 #define IO_TO_VIRT_XLATE(p, pst, vst)   (((p) - (pst) + (vst)))
0115
0116 #define IO_TO_VIRT(n) ( \
0117     IO_TO_VIRT_BETWEEN((n), IO_PPSB_PHYS, IO_PPSB_SIZE) ?       \
0118         IO_TO_VIRT_XLATE((n), IO_PPSB_PHYS, IO_PPSB_VIRT) : \
0119     IO_TO_VIRT_BETWEEN((n), IO_APB_PHYS, IO_APB_SIZE) ?     \
0120         IO_TO_VIRT_XLATE((n), IO_APB_PHYS, IO_APB_VIRT) :   \
0121     IO_TO_VIRT_BETWEEN((n), IO_CPU_PHYS, IO_CPU_SIZE) ?     \
0122         IO_TO_VIRT_XLATE((n), IO_CPU_PHYS, IO_CPU_VIRT) :   \
0123     IO_TO_VIRT_BETWEEN((n), IO_IRAM_PHYS, IO_IRAM_SIZE) ?       \
0124         IO_TO_VIRT_XLATE((n), IO_IRAM_PHYS, IO_IRAM_VIRT) : \
0125     NULL)
0126
0127 #define IO_ADDRESS(n) (IO_TO_VIRT(n))
0128
0129 #endif