arm/mach-sunxi/headsmp.S

0001 /* SPDX-License-Identifier: GPL-2.0
0002  *
0003  * Copyright (c) 2018 Chen-Yu Tsai
0004  * Copyright (c) 2018 Bootlin
0005  *
0006  * Chen-Yu Tsai <wens@csie.org>
0007  * Mylène Josserand <mylene.josserand@bootlin.com>
0008  *
0009  * SMP support for sunxi based systems with Cortex A7/A15
0010  *
0011  */
0012
0013 #include <linux/linkage.h>
0014 #include <asm/assembler.h>
0015 #include <asm/cputype.h>
0016
0017 ENTRY(sunxi_mc_smp_cluster_cache_enable)
0018     .arch   armv7-a
0019     /*
0020      * Enable cluster-level coherency, in preparation for turning on the MMU.
0021      *
0022      * Also enable regional clock gating and L2 data latency settings for
0023      * Cortex-A15. These settings are from the vendor kernel.
0024      */
0025     mrc p15, 0, r1, c0, c0, 0
0026     movw    r2, #(ARM_CPU_PART_MASK & 0xffff)
0027     movt    r2, #(ARM_CPU_PART_MASK >> 16)
0028     and r1, r1, r2
0029     movw    r2, #(ARM_CPU_PART_CORTEX_A15 & 0xffff)
0030     movt    r2, #(ARM_CPU_PART_CORTEX_A15 >> 16)
0031     cmp r1, r2
0032     bne not_a15
0033
0034     /* The following is Cortex-A15 specific */
0035
0036     /* ACTLR2: Enable CPU regional clock gates */
0037     mrc p15, 1, r1, c15, c0, 4
0038     orr r1, r1, #(0x1 << 31)
0039     mcr p15, 1, r1, c15, c0, 4
0040
0041     /* L2ACTLR */
0042     mrc p15, 1, r1, c15, c0, 0
0043     /* Enable L2, GIC, and Timer regional clock gates */
0044     orr r1, r1, #(0x1 << 26)
0045     /* Disable clean/evict from being pushed to external */
0046     orr r1, r1, #(0x1<<3)
0047     mcr p15, 1, r1, c15, c0, 0
0048
0049     /* L2CTRL: L2 data RAM latency */
0050     mrc p15, 1, r1, c9, c0, 2
0051     bic r1, r1, #(0x7 << 0)
0052     orr r1, r1, #(0x3 << 0)
0053     mcr p15, 1, r1, c9, c0, 2
0054
0055     /* End of Cortex-A15 specific setup */
0056     not_a15:
0057
0058     /* Get value of sunxi_mc_smp_first_comer */
0059     adr r1, first
0060     ldr r0, [r1]
0061     ldr r0, [r1, r0]
0062
0063     /* Skip cci_enable_port_for_self if not first comer */
0064     cmp r0, #0
0065     bxeq    lr
0066     b   cci_enable_port_for_self
0067
0068     .align 2
0069     first: .word sunxi_mc_smp_first_comer - .
0070 ENDPROC(sunxi_mc_smp_cluster_cache_enable)
0071
0072 ENTRY(sunxi_mc_smp_secondary_startup)
0073     bl  sunxi_mc_smp_cluster_cache_enable
0074     bl  secure_cntvoff_init
0075     b   secondary_startup
0076 ENDPROC(sunxi_mc_smp_secondary_startup)
0077
0078 ENTRY(sunxi_mc_smp_resume)
0079     bl  sunxi_mc_smp_cluster_cache_enable
0080     b   cpu_resume
0081 ENDPROC(sunxi_mc_smp_resume)