arm/mach-spear/time.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * arch/arm/plat-spear/time.c
0004  *
0005  * Copyright (C) 2010 ST Microelectronics
0006  * Shiraz Hashim<shiraz.linux.kernel@gmail.com>
0007  */
0008
0009 #include <linux/clk.h>
0010 #include <linux/clockchips.h>
0011 #include <linux/clocksource.h>
0012 #include <linux/err.h>
0013 #include <linux/init.h>
0014 #include <linux/interrupt.h>
0015 #include <linux/ioport.h>
0016 #include <linux/io.h>
0017 #include <linux/kernel.h>
0018 #include <linux/of_irq.h>
0019 #include <linux/of_address.h>
0020 #include <linux/time.h>
0021 #include <linux/irq.h>
0022 #include <asm/mach/time.h>
0023 #include "generic.h"
0024
0025 /*
0026  * We would use TIMER0 and TIMER1 as clockevent and clocksource.
0027  * Timer0 and Timer1 both belong to same gpt block in cpu subbsystem. Further
0028  * they share same functional clock. Any change in one's functional clock will
0029  * also affect other timer.
0030  */
0031
0032 #define CLKEVT  0   /* gpt0, channel0 as clockevent */
0033 #define CLKSRC  1   /* gpt0, channel1 as clocksource */
0034
0035 /* Register offsets, x is channel number */
0036 #define CR(x)       ((x) * 0x80 + 0x80)
0037 #define IR(x)       ((x) * 0x80 + 0x84)
0038 #define LOAD(x)     ((x) * 0x80 + 0x88)
0039 #define COUNT(x)    ((x) * 0x80 + 0x8C)
0040
0041 /* Reg bit definitions */
0042 #define CTRL_INT_ENABLE     0x0100
0043 #define CTRL_ENABLE     0x0020
0044 #define CTRL_ONE_SHOT       0x0010
0045
0046 #define CTRL_PRESCALER1     0x0
0047 #define CTRL_PRESCALER2     0x1
0048 #define CTRL_PRESCALER4     0x2
0049 #define CTRL_PRESCALER8     0x3
0050 #define CTRL_PRESCALER16    0x4
0051 #define CTRL_PRESCALER32    0x5
0052 #define CTRL_PRESCALER64    0x6
0053 #define CTRL_PRESCALER128   0x7
0054 #define CTRL_PRESCALER256   0x8
0055
0056 #define INT_STATUS      0x1
0057
0058 /*
0059  * Minimum clocksource/clockevent timer range in seconds
0060  */
0061 #define SPEAR_MIN_RANGE 4
0062
0063 static __iomem void *gpt_base;
0064 static struct clk *gpt_clk;
0065
0066 static int clockevent_next_event(unsigned long evt,
0067                  struct clock_event_device *clk_event_dev);
0068
0069 static void __init spear_clocksource_init(void)
0070 {
0071     u32 tick_rate;
0072     u16 val;
0073
0074     /* program the prescaler (/256)*/
0075     writew(CTRL_PRESCALER256, gpt_base + CR(CLKSRC));
0076
0077     /* find out actual clock driving Timer */
0078     tick_rate = clk_get_rate(gpt_clk);
0079     tick_rate >>= CTRL_PRESCALER256;
0080
0081     writew(0xFFFF, gpt_base + LOAD(CLKSRC));
0082
0083     val = readw(gpt_base + CR(CLKSRC));
0084     val &= ~CTRL_ONE_SHOT;  /* autoreload mode */
0085     val |= CTRL_ENABLE ;
0086     writew(val, gpt_base + CR(CLKSRC));
0087
0088     /* register the clocksource */
0089     clocksource_mmio_init(gpt_base + COUNT(CLKSRC), "tmr1", tick_rate,
0090         200, 16, clocksource_mmio_readw_up);
0091 }
0092
0093 static inline void timer_shutdown(struct clock_event_device *evt)
0094 {
0095     u16 val = readw(gpt_base + CR(CLKEVT));
0096
0097     /* stop the timer */
0098     val &= ~CTRL_ENABLE;
0099     writew(val, gpt_base + CR(CLKEVT));
0100 }
0101
0102 static int spear_shutdown(struct clock_event_device *evt)
0103 {
0104     timer_shutdown(evt);
0105
0106     return 0;
0107 }
0108
0109 static int spear_set_oneshot(struct clock_event_device *evt)
0110 {
0111     u16 val;
0112
0113     /* stop the timer */
0114     timer_shutdown(evt);
0115
0116     val = readw(gpt_base + CR(CLKEVT));
0117     val |= CTRL_ONE_SHOT;
0118     writew(val, gpt_base + CR(CLKEVT));
0119
0120     return 0;
0121 }
0122
0123 static int spear_set_periodic(struct clock_event_device *evt)
0124 {
0125     u32 period;
0126     u16 val;
0127
0128     /* stop the timer */
0129     timer_shutdown(evt);
0130
0131     period = clk_get_rate(gpt_clk) / HZ;
0132     period >>= CTRL_PRESCALER16;
0133     writew(period, gpt_base + LOAD(CLKEVT));
0134
0135     val = readw(gpt_base + CR(CLKEVT));
0136     val &= ~CTRL_ONE_SHOT;
0137     val |= CTRL_ENABLE | CTRL_INT_ENABLE;
0138     writew(val, gpt_base + CR(CLKEVT));
0139
0140     return 0;
0141 }
0142
0143 static struct clock_event_device clkevt = {
0144     .name = "tmr0",
0145     .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
0146     .set_state_shutdown = spear_shutdown,
0147     .set_state_periodic = spear_set_periodic,
0148     .set_state_oneshot = spear_set_oneshot,
0149     .tick_resume = spear_shutdown,
0150     .set_next_event = clockevent_next_event,
0151     .shift = 0, /* to be computed */
0152 };
0153
0154 static int clockevent_next_event(unsigned long cycles,
0155                  struct clock_event_device *clk_event_dev)
0156 {
0157     u16 val = readw(gpt_base + CR(CLKEVT));
0158
0159     if (val & CTRL_ENABLE)
0160         writew(val & ~CTRL_ENABLE, gpt_base + CR(CLKEVT));
0161
0162     writew(cycles, gpt_base + LOAD(CLKEVT));
0163
0164     val |= CTRL_ENABLE | CTRL_INT_ENABLE;
0165     writew(val, gpt_base + CR(CLKEVT));
0166
0167     return 0;
0168 }
0169
0170 static irqreturn_t spear_timer_interrupt(int irq, void *dev_id)
0171 {
0172     struct clock_event_device *evt = &clkevt;
0173
0174     writew(INT_STATUS, gpt_base + IR(CLKEVT));
0175
0176     evt->event_handler(evt);
0177
0178     return IRQ_HANDLED;
0179 }
0180
0181 static void __init spear_clockevent_init(int irq)
0182 {
0183     u32 tick_rate;
0184
0185     /* program the prescaler */
0186     writew(CTRL_PRESCALER16, gpt_base + CR(CLKEVT));
0187
0188     tick_rate = clk_get_rate(gpt_clk);
0189     tick_rate >>= CTRL_PRESCALER16;
0190
0191     clkevt.cpumask = cpumask_of(0);
0192
0193     clockevents_config_and_register(&clkevt, tick_rate, 3, 0xfff0);
0194
0195     if (request_irq(irq, spear_timer_interrupt, IRQF_TIMER, "timer", NULL))
0196         pr_err("Failed to request irq %d (timer)\n", irq);
0197 }
0198
0199 static const struct of_device_id timer_of_match[] __initconst = {
0200     { .compatible = "st,spear-timer", },
0201     { },
0202 };
0203
0204 void __init spear_setup_of_timer(void)
0205 {
0206     struct device_node *np;
0207     int irq, ret;
0208
0209     np = of_find_matching_node(NULL, timer_of_match);
0210     if (!np) {
0211         pr_err("%s: No timer passed via DT\n", __func__);
0212         return;
0213     }
0214
0215     irq = irq_of_parse_and_map(np, 0);
0216     if (!irq) {
0217         pr_err("%s: No irq passed for timer via DT\n", __func__);
0218         goto err_put_np;
0219     }
0220
0221     gpt_base = of_iomap(np, 0);
0222     if (!gpt_base) {
0223         pr_err("%s: of iomap failed\n", __func__);
0224         goto err_put_np;
0225     }
0226
0227     gpt_clk = clk_get_sys("gpt0", NULL);
0228     if (IS_ERR(gpt_clk)) {
0229         pr_err("%s:couldn't get clk for gpt\n", __func__);
0230         goto err_iomap;
0231     }
0232
0233     ret = clk_prepare_enable(gpt_clk);
0234     if (ret < 0) {
0235         pr_err("%s:couldn't prepare-enable gpt clock\n", __func__);
0236         goto err_prepare_enable_clk;
0237     }
0238
0239     of_node_put(np);
0240
0241     spear_clockevent_init(irq);
0242     spear_clocksource_init();
0243
0244     return;
0245
0246 err_prepare_enable_clk:
0247     clk_put(gpt_clk);
0248 err_iomap:
0249     iounmap(gpt_base);
0250 err_put_np:
0251     of_node_put(np);
0252 }