arm/mach-spear/spear13xx.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * arch/arm/mach-spear13xx/spear13xx.c
0004  *
0005  * SPEAr13XX machines common source file
0006  *
0007  * Copyright (C) 2012 ST Microelectronics
0008  * Viresh Kumar <vireshk@kernel.org>
0009  */
0010
0011 #define pr_fmt(fmt) "SPEAr13xx: " fmt
0012
0013 #include <linux/amba/pl022.h>
0014 #include <linux/clk.h>
0015 #include <linux/clk/spear.h>
0016 #include <linux/clocksource.h>
0017 #include <linux/err.h>
0018 #include <linux/of.h>
0019 #include <asm/hardware/cache-l2x0.h>
0020 #include <asm/mach/map.h>
0021 #include "spear.h"
0022 #include "generic.h"
0023
0024 void __init spear13xx_l2x0_init(void)
0025 {
0026     /*
0027      * 512KB (64KB/way), 8-way associativity, parity supported
0028      *
0029      * FIXME: 9th bit, of Auxiliary Controller register must be set
0030      * for some spear13xx devices for stable L2 operation.
0031      *
0032      * Enable Early BRESP, L2 prefetch for Instruction and Data,
0033      * write alloc and 'Full line of zero' options
0034      *
0035      */
0036     if (!IS_ENABLED(CONFIG_CACHE_L2X0))
0037         return;
0038
0039     writel_relaxed(0x06, VA_L2CC_BASE + L310_PREFETCH_CTRL);
0040
0041     /*
0042      * Program following latencies in order to make
0043      * SPEAr1340 work at 600 MHz
0044      */
0045     writel_relaxed(0x221, VA_L2CC_BASE + L310_TAG_LATENCY_CTRL);
0046     writel_relaxed(0x441, VA_L2CC_BASE + L310_DATA_LATENCY_CTRL);
0047     l2x0_init(VA_L2CC_BASE, 0x30a00001, 0xfe0fffff);
0048 }
0049
0050 /*
0051  * Following will create 16MB static virtual/physical mappings
0052  * PHYSICAL     VIRTUAL
0053  * 0xB3000000       0xF9000000
0054  * 0xE0000000       0xFD000000
0055  * 0xEC000000       0xFC000000
0056  * 0xED000000       0xFB000000
0057  */
0058 static struct map_desc spear13xx_io_desc[] __initdata = {
0059     {
0060         .virtual    = (unsigned long)VA_PERIP_GRP2_BASE,
0061         .pfn        = __phys_to_pfn(PERIP_GRP2_BASE),
0062         .length     = SZ_16M,
0063         .type       = MT_DEVICE
0064     }, {
0065         .virtual    = (unsigned long)VA_PERIP_GRP1_BASE,
0066         .pfn        = __phys_to_pfn(PERIP_GRP1_BASE),
0067         .length     = SZ_16M,
0068         .type       = MT_DEVICE
0069     }, {
0070         .virtual    = (unsigned long)VA_A9SM_AND_MPMC_BASE,
0071         .pfn        = __phys_to_pfn(A9SM_AND_MPMC_BASE),
0072         .length     = SZ_16M,
0073         .type       = MT_DEVICE
0074     }, {
0075         .virtual    = (unsigned long)VA_L2CC_BASE,
0076         .pfn        = __phys_to_pfn(L2CC_BASE),
0077         .length     = SZ_4K,
0078         .type       = MT_DEVICE
0079     },
0080 };
0081
0082 /* This will create static memory mapping for selected devices */
0083 void __init spear13xx_map_io(void)
0084 {
0085     iotable_init(spear13xx_io_desc, ARRAY_SIZE(spear13xx_io_desc));
0086 }
0087
0088 static void __init spear13xx_clk_init(void)
0089 {
0090     if (of_machine_is_compatible("st,spear1310"))
0091         spear1310_clk_init(VA_MISC_BASE, VA_SPEAR1310_RAS_BASE);
0092     else if (of_machine_is_compatible("st,spear1340"))
0093         spear1340_clk_init(VA_MISC_BASE);
0094     else
0095         pr_err("%s: Unknown machine\n", __func__);
0096 }
0097
0098 void __init spear13xx_timer_init(void)
0099 {
0100     char pclk_name[] = "osc_24m_clk";
0101     struct clk *gpt_clk, *pclk;
0102
0103     spear13xx_clk_init();
0104
0105     /* get the system timer clock */
0106     gpt_clk = clk_get_sys("gpt0", NULL);
0107     if (IS_ERR(gpt_clk)) {
0108         pr_err("%s:couldn't get clk for gpt\n", __func__);
0109         BUG();
0110     }
0111
0112     /* get the suitable parent clock for timer*/
0113     pclk = clk_get(NULL, pclk_name);
0114     if (IS_ERR(pclk)) {
0115         pr_err("%s:couldn't get %s as parent for gpt\n", __func__,
0116                 pclk_name);
0117         BUG();
0118     }
0119
0120     clk_set_parent(gpt_clk, pclk);
0121     clk_put(gpt_clk);
0122     clk_put(pclk);
0123
0124     spear_setup_of_timer();
0125     timer_probe();
0126 }