arm/mach-socfpga/socfpga.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  *  Copyright (C) 2012-2015 Altera Corporation
0004  */
0005 #include <linux/irqchip.h>
0006 #include <linux/of_address.h>
0007 #include <linux/of_irq.h>
0008 #include <linux/of_platform.h>
0009 #include <linux/reboot.h>
0010 #include <linux/reset/socfpga.h>
0011
0012 #include <asm/hardware/cache-l2x0.h>
0013 #include <asm/mach/arch.h>
0014 #include <asm/mach/map.h>
0015 #include <asm/cacheflush.h>
0016
0017 #include "core.h"
0018
0019 void __iomem *sys_manager_base_addr;
0020 void __iomem *rst_manager_base_addr;
0021 void __iomem *sdr_ctl_base_addr;
0022 unsigned long socfpga_cpu1start_addr;
0023
0024 static void __init socfpga_sysmgr_init(void)
0025 {
0026     struct device_node *np;
0027
0028     np = of_find_compatible_node(NULL, NULL, "altr,sys-mgr");
0029
0030     if (of_property_read_u32(np, "cpu1-start-addr",
0031             (u32 *) &socfpga_cpu1start_addr))
0032         pr_err("SMP: Need cpu1-start-addr in device tree.\n");
0033
0034     /* Ensure that socfpga_cpu1start_addr is visible to other CPUs */
0035     smp_wmb();
0036     sync_cache_w(&socfpga_cpu1start_addr);
0037
0038     sys_manager_base_addr = of_iomap(np, 0);
0039
0040     np = of_find_compatible_node(NULL, NULL, "altr,rst-mgr");
0041     rst_manager_base_addr = of_iomap(np, 0);
0042
0043     np = of_find_compatible_node(NULL, NULL, "altr,sdr-ctl");
0044     sdr_ctl_base_addr = of_iomap(np, 0);
0045 }
0046
0047 static void __init socfpga_init_irq(void)
0048 {
0049     irqchip_init();
0050     socfpga_sysmgr_init();
0051     if (IS_ENABLED(CONFIG_EDAC_ALTERA_L2C))
0052         socfpga_init_l2_ecc();
0053
0054     if (IS_ENABLED(CONFIG_EDAC_ALTERA_OCRAM))
0055         socfpga_init_ocram_ecc();
0056     socfpga_reset_init();
0057 }
0058
0059 static void __init socfpga_arria10_init_irq(void)
0060 {
0061     irqchip_init();
0062     socfpga_sysmgr_init();
0063     if (IS_ENABLED(CONFIG_EDAC_ALTERA_L2C))
0064         socfpga_init_arria10_l2_ecc();
0065     if (IS_ENABLED(CONFIG_EDAC_ALTERA_OCRAM))
0066         socfpga_init_arria10_ocram_ecc();
0067     socfpga_reset_init();
0068 }
0069
0070 static void socfpga_cyclone5_restart(enum reboot_mode mode, const char *cmd)
0071 {
0072     u32 temp;
0073
0074     temp = readl(rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL);
0075
0076     if (mode == REBOOT_WARM)
0077         temp |= RSTMGR_CTRL_SWWARMRSTREQ;
0078     else
0079         temp |= RSTMGR_CTRL_SWCOLDRSTREQ;
0080     writel(temp, rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL);
0081 }
0082
0083 static void socfpga_arria10_restart(enum reboot_mode mode, const char *cmd)
0084 {
0085     u32 temp;
0086
0087     temp = readl(rst_manager_base_addr + SOCFPGA_A10_RSTMGR_CTRL);
0088
0089     if (mode == REBOOT_WARM)
0090         temp |= RSTMGR_CTRL_SWWARMRSTREQ;
0091     else
0092         temp |= RSTMGR_CTRL_SWCOLDRSTREQ;
0093     writel(temp, rst_manager_base_addr + SOCFPGA_A10_RSTMGR_CTRL);
0094 }
0095
0096 static const char *altera_dt_match[] = {
0097     "altr,socfpga",
0098     NULL
0099 };
0100
0101 DT_MACHINE_START(SOCFPGA, "Altera SOCFPGA")
0102     .l2c_aux_val    = 0,
0103     .l2c_aux_mask   = ~0,
0104     .init_irq   = socfpga_init_irq,
0105     .restart    = socfpga_cyclone5_restart,
0106     .dt_compat  = altera_dt_match,
0107 MACHINE_END
0108
0109 static const char *altera_a10_dt_match[] = {
0110     "altr,socfpga-arria10",
0111     NULL
0112 };
0113
0114 DT_MACHINE_START(SOCFPGA_A10, "Altera SOCFPGA Arria10")
0115     .l2c_aux_val    = 0,
0116     .l2c_aux_mask   = ~0,
0117     .init_irq   = socfpga_arria10_init_irq,
0118     .restart    = socfpga_arria10_restart,
0119     .dt_compat  = altera_a10_dt_match,
0120 MACHINE_END