arm/mach-socfpga/core.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Copyright 2012 Pavel Machek <pavel@denx.de>
0004  * Copyright (C) 2012-2015 Altera Corporation
0005  */
0006
0007 #ifndef __MACH_CORE_H
0008 #define __MACH_CORE_H
0009
0010 #define SOCFPGA_RSTMGR_CTRL 0x04
0011 #define SOCFPGA_RSTMGR_MODMPURST    0x10
0012 #define SOCFPGA_RSTMGR_MODPERRST    0x14
0013 #define SOCFPGA_RSTMGR_BRGMODRST    0x1c
0014
0015 #define SOCFPGA_A10_RSTMGR_CTRL     0xC
0016 #define SOCFPGA_A10_RSTMGR_MODMPURST    0x20
0017
0018 /* System Manager bits */
0019 #define RSTMGR_CTRL_SWCOLDRSTREQ    0x1 /* Cold Reset */
0020 #define RSTMGR_CTRL_SWWARMRSTREQ    0x2 /* Warm Reset */
0021
0022 #define RSTMGR_MPUMODRST_CPU1       0x2     /* CPU1 Reset */
0023
0024 void socfpga_init_l2_ecc(void);
0025 void socfpga_init_ocram_ecc(void);
0026 void socfpga_init_arria10_l2_ecc(void);
0027 void socfpga_init_arria10_ocram_ecc(void);
0028
0029 extern void __iomem *sys_manager_base_addr;
0030 extern void __iomem *rst_manager_base_addr;
0031 extern void __iomem *sdr_ctl_base_addr;
0032
0033 u32 socfpga_sdram_self_refresh(u32 sdr_base);
0034 extern unsigned int socfpga_sdram_self_refresh_sz;
0035
0036 extern char secondary_trampoline[], secondary_trampoline_end[];
0037
0038 extern unsigned long socfpga_cpu1start_addr;
0039
0040 #define SOCFPGA_SCU_VIRT_BASE   0xfee00000
0041
0042 #endif