arm/mach-shmobile/pm-rcar-gen2.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * R-Car Generation 2 Power management support
0004  *
0005  * Copyright (C) 2013 - 2015  Renesas Electronics Corporation
0006  * Copyright (C) 2011  Renesas Solutions Corp.
0007  * Copyright (C) 2011  Magnus Damm
0008  */
0009
0010 #include <linux/kernel.h>
0011 #include <linux/ioport.h>
0012 #include <linux/of.h>
0013 #include <linux/of_address.h>
0014 #include <linux/smp.h>
0015 #include <asm/io.h>
0016 #include <asm/cputype.h>
0017 #include "common.h"
0018 #include "rcar-gen2.h"
0019
0020 /* RST */
0021 #define RST     0xe6160000
0022
0023 #define CA15BAR     0x0020      /* CA15 Boot Address Register */
0024 #define CA7BAR      0x0030      /* CA7 Boot Address Register */
0025 #define CA15RESCNT  0x0040      /* CA15 Reset Control Register */
0026 #define CA7RESCNT   0x0044      /* CA7 Reset Control Register */
0027
0028 /* SYS Boot Address Register */
0029 #define SBAR_BAREN  BIT(4)      /* SBAR is valid */
0030
0031 /* Reset Control Registers */
0032 #define CA15RESCNT_CODE 0xa5a50000
0033 #define CA15RESCNT_CPUS 0xf     /* CPU0-3 */
0034 #define CA7RESCNT_CODE  0x5a5a0000
0035 #define CA7RESCNT_CPUS  0xf     /* CPU0-3 */
0036
0037 /* On-chip RAM */
0038 #define ICRAM1      0xe63c0000  /* Inter Connect RAM1 (4 KiB) */
0039
0040 static inline u32 phys_to_sbar(phys_addr_t addr)
0041 {
0042     return (addr >> 8) & 0xfffffc00;
0043 }
0044
0045 void __init rcar_gen2_pm_init(void)
0046 {
0047     void __iomem *p;
0048     u32 bar;
0049     static int once;
0050     struct device_node *np;
0051     bool has_a7 = false;
0052     bool has_a15 = false;
0053     struct resource res;
0054     int error;
0055
0056     if (once++)
0057         return;
0058
0059     for_each_of_cpu_node(np) {
0060         if (of_device_is_compatible(np, "arm,cortex-a15"))
0061             has_a15 = true;
0062         else if (of_device_is_compatible(np, "arm,cortex-a7"))
0063             has_a7 = true;
0064     }
0065
0066     np = of_find_compatible_node(NULL, NULL, "renesas,smp-sram");
0067     if (!np) {
0068         /* No smp-sram in DT, fall back to hardcoded address */
0069         res = (struct resource)DEFINE_RES_MEM(ICRAM1,
0070                               shmobile_boot_size);
0071         goto map;
0072     }
0073
0074     error = of_address_to_resource(np, 0, &res);
0075     of_node_put(np);
0076     if (error) {
0077         pr_err("Failed to get smp-sram address: %d\n", error);
0078         return;
0079     }
0080
0081 map:
0082     /* RAM for jump stub, because BAR requires 256KB aligned address */
0083     if (res.start & (256 * 1024 - 1) ||
0084         resource_size(&res) < shmobile_boot_size) {
0085         pr_err("Invalid smp-sram region\n");
0086         return;
0087     }
0088
0089     p = ioremap(res.start, resource_size(&res));
0090     if (!p)
0091         return;
0092     /*
0093      * install the reset vector, use the largest version if we have enough
0094      * memory available
0095      */
0096     if (resource_size(&res) >= shmobile_boot_size_gen2) {
0097         shmobile_boot_cpu_gen2 = read_cpuid_mpidr();
0098         memcpy_toio(p, shmobile_boot_vector_gen2,
0099                 shmobile_boot_size_gen2);
0100     } else {
0101         memcpy_toio(p, shmobile_boot_vector, shmobile_boot_size);
0102     }
0103     iounmap(p);
0104
0105     /* setup reset vectors */
0106     p = ioremap(RST, 0x63);
0107     bar = phys_to_sbar(res.start);
0108     if (has_a15) {
0109         writel_relaxed(bar, p + CA15BAR);
0110         writel_relaxed(bar | SBAR_BAREN, p + CA15BAR);
0111
0112         /* de-assert reset for CA15 CPUs */
0113         writel_relaxed((readl_relaxed(p + CA15RESCNT) &
0114                 ~CA15RESCNT_CPUS) | CA15RESCNT_CODE,
0115                    p + CA15RESCNT);
0116     }
0117     if (has_a7) {
0118         writel_relaxed(bar, p + CA7BAR);
0119         writel_relaxed(bar | SBAR_BAREN, p + CA7BAR);
0120
0121         /* de-assert reset for CA7 CPUs */
0122         writel_relaxed((readl_relaxed(p + CA7RESCNT) &
0123                 ~CA7RESCNT_CPUS) | CA7RESCNT_CODE,
0124                    p + CA7RESCNT);
0125     }
0126     iounmap(p);
0127
0128     shmobile_smp_apmu_suspend_init();
0129 }