arm/mach-shmobile/headsmp-scu.S

0001 /* SPDX-License-Identifier: GPL-2.0+
0002  *
0003  * Shared SCU setup for mach-shmobile
0004  *
0005  * Copyright (C) 2012 Bastian Hecht
0006  */
0007
0008 #include <linux/linkage.h>
0009 #include <linux/init.h>
0010 #include <asm/memory.h>
0011
0012 /*
0013  * Boot code for secondary CPUs.
0014  *
0015  * First we turn on L1 cache coherency for our CPU. Then we jump to
0016  * secondary_startup that invalidates the cache and hands over control
0017  * to the common ARM startup code.
0018  */
0019 ENTRY(shmobile_boot_scu)
0020                     @ r0 = SCU base address
0021     mrc     p15, 0, r1, c0, c0, 5   @ read MPIDR
0022     and r1, r1, #3      @ mask out cpu ID
0023     lsl r1, r1, #3      @ we will shift by cpu_id * 8 bits
0024     ldr r2, [r0, #8]        @ SCU Power Status Register
0025     mov r3, #3
0026     lsl r3, r3, r1
0027     bic r2, r2, r3      @ Clear bits of our CPU (Run Mode)
0028     str r2, [r0, #8]        @ write back
0029
0030     b   secondary_startup
0031 ENDPROC(shmobile_boot_scu)