arm/mach-sa1100/pci-nanoengine.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * linux/arch/arm/mach-sa1100/pci-nanoengine.c
0004  *
0005  * PCI functions for BSE nanoEngine PCI
0006  *
0007  * Copyright (C) 2010 Marcelo Roberto Jimenez <mroberto@cpti.cetuc.puc-rio.br>
0008  */
0009 #include <linux/kernel.h>
0010 #include <linux/irq.h>
0011 #include <linux/pci.h>
0012
0013 #include <asm/mach/pci.h>
0014 #include <asm/mach-types.h>
0015
0016 #include <mach/nanoengine.h>
0017 #include <mach/hardware.h>
0018
0019 static void __iomem *nanoengine_pci_map_bus(struct pci_bus *bus,
0020                         unsigned int devfn, int where)
0021 {
0022     if (bus->number != 0 || (devfn >> 3) != 0)
0023         return NULL;
0024
0025     return (void __iomem *)NANO_PCI_CONFIG_SPACE_VIRT +
0026         ((bus->number << 16) | (devfn << 8) | (where & ~3));
0027 }
0028
0029 static struct pci_ops pci_nano_ops = {
0030     .map_bus = nanoengine_pci_map_bus,
0031     .read   = pci_generic_config_read32,
0032     .write  = pci_generic_config_write32,
0033 };
0034
0035 static int __init pci_nanoengine_map_irq(const struct pci_dev *dev, u8 slot,
0036     u8 pin)
0037 {
0038     return NANOENGINE_IRQ_GPIO_PCI;
0039 }
0040
0041 static struct resource pci_io_ports =
0042     DEFINE_RES_IO_NAMED(0x400, 0x400, "PCI IO");
0043
0044 static struct resource pci_non_prefetchable_memory = {
0045     .name   = "PCI non-prefetchable",
0046     .start  = NANO_PCI_MEM_RW_PHYS,
0047     /* nanoEngine documentation says there is a 1 Megabyte window here,
0048      * but PCI reports just 128 + 8 kbytes. */
0049     .end    = NANO_PCI_MEM_RW_PHYS + NANO_PCI_MEM_RW_SIZE - 1,
0050 /*  .end    = NANO_PCI_MEM_RW_PHYS + SZ_128K + SZ_8K - 1,*/
0051     .flags  = IORESOURCE_MEM,
0052 };
0053
0054 /*
0055  * nanoEngine PCI reports 1 Megabyte of prefetchable memory, but it
0056  * overlaps with previously defined memory.
0057  *
0058  * Here is what happens:
0059  *
0060 # dmesg
0061 ...
0062 pci 0000:00:00.0: [8086:1209] type 0 class 0x000200
0063 pci 0000:00:00.0: reg 10: [mem 0x00021000-0x00021fff]
0064 pci 0000:00:00.0: reg 14: [io  0x0000-0x003f]
0065 pci 0000:00:00.0: reg 18: [mem 0x00000000-0x0001ffff]
0066 pci 0000:00:00.0: reg 30: [mem 0x00000000-0x000fffff pref]
0067 pci 0000:00:00.0: supports D1 D2
0068 pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot
0069 pci 0000:00:00.0: PME# disabled
0070 PCI: bus0: Fast back to back transfers enabled
0071 pci 0000:00:00.0: BAR 6: can't assign mem pref (size 0x100000)
0072 pci 0000:00:00.0: BAR 2: assigned [mem 0x18600000-0x1861ffff]
0073 pci 0000:00:00.0: BAR 2: set to [mem 0x18600000-0x1861ffff] (PCI address [0x0-0x1ffff])
0074 pci 0000:00:00.0: BAR 0: assigned [mem 0x18620000-0x18620fff]
0075 pci 0000:00:00.0: BAR 0: set to [mem 0x18620000-0x18620fff] (PCI address [0x20000-0x20fff])
0076 pci 0000:00:00.0: BAR 1: assigned [io  0x0400-0x043f]
0077 pci 0000:00:00.0: BAR 1: set to [io  0x0400-0x043f] (PCI address [0x0-0x3f])
0078  *
0079  * On the other hand, if we do not request the prefetchable memory resource,
0080  * linux will alloc it first and the two non-prefetchable memory areas that
0081  * are our real interest will not be mapped. So we choose to map it to an
0082  * unused area. It gets recognized as expansion ROM, but becomes disabled.
0083  *
0084  * Here is what happens then:
0085  *
0086 # dmesg
0087 ...
0088 pci 0000:00:00.0: [8086:1209] type 0 class 0x000200
0089 pci 0000:00:00.0: reg 10: [mem 0x00021000-0x00021fff]
0090 pci 0000:00:00.0: reg 14: [io  0x0000-0x003f]
0091 pci 0000:00:00.0: reg 18: [mem 0x00000000-0x0001ffff]
0092 pci 0000:00:00.0: reg 30: [mem 0x00000000-0x000fffff pref]
0093 pci 0000:00:00.0: supports D1 D2
0094 pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot
0095 pci 0000:00:00.0: PME# disabled
0096 PCI: bus0: Fast back to back transfers enabled
0097 pci 0000:00:00.0: BAR 6: assigned [mem 0x78000000-0x780fffff pref]
0098 pci 0000:00:00.0: BAR 2: assigned [mem 0x18600000-0x1861ffff]
0099 pci 0000:00:00.0: BAR 2: set to [mem 0x18600000-0x1861ffff] (PCI address [0x0-0x1ffff])
0100 pci 0000:00:00.0: BAR 0: assigned [mem 0x18620000-0x18620fff]
0101 pci 0000:00:00.0: BAR 0: set to [mem 0x18620000-0x18620fff] (PCI address [0x20000-0x20fff])
0102 pci 0000:00:00.0: BAR 1: assigned [io  0x0400-0x043f]
0103 pci 0000:00:00.0: BAR 1: set to [io  0x0400-0x043f] (PCI address [0x0-0x3f])
0104
0105 # lspci -vv -s 0000:00:00.0
0106 00:00.0 Class 0200: Device 8086:1209 (rev 09)
0107         Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx-
0108         Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR+ <PERR+ INTx-
0109         Latency: 0 (2000ns min, 14000ns max), Cache Line Size: 32 bytes
0110         Interrupt: pin A routed to IRQ 0
0111         Region 0: Memory at 18620000 (32-bit, non-prefetchable) [size=4K]
0112         Region 1: I/O ports at 0400 [size=64]
0113         Region 2: [virtual] Memory at 18600000 (32-bit, non-prefetchable) [size=128K]
0114         [virtual] Expansion ROM at 78000000 [disabled] [size=1M]
0115         Capabilities: [dc] Power Management version 2
0116                 Flags: PMEClk- DSI+ D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-)
0117                 Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=2 PME-
0118         Kernel driver in use: e100
0119         Kernel modules: e100
0120  *
0121  */
0122 static struct resource pci_prefetchable_memory = {
0123     .name   = "PCI prefetchable",
0124     .start  = 0x78000000,
0125     .end    = 0x78000000 + NANO_PCI_MEM_RW_SIZE - 1,
0126     .flags  = IORESOURCE_MEM  | IORESOURCE_PREFETCH,
0127 };
0128
0129 static int __init pci_nanoengine_setup_resources(struct pci_sys_data *sys)
0130 {
0131     if (request_resource(&ioport_resource, &pci_io_ports)) {
0132         printk(KERN_ERR "PCI: unable to allocate io port region\n");
0133         return -EBUSY;
0134     }
0135     if (request_resource(&iomem_resource, &pci_non_prefetchable_memory)) {
0136         release_resource(&pci_io_ports);
0137         printk(KERN_ERR "PCI: unable to allocate non prefetchable\n");
0138         return -EBUSY;
0139     }
0140     if (request_resource(&iomem_resource, &pci_prefetchable_memory)) {
0141         release_resource(&pci_io_ports);
0142         release_resource(&pci_non_prefetchable_memory);
0143         printk(KERN_ERR "PCI: unable to allocate prefetchable\n");
0144         return -EBUSY;
0145     }
0146     pci_add_resource_offset(&sys->resources, &pci_io_ports, sys->io_offset);
0147     pci_add_resource_offset(&sys->resources,
0148                 &pci_non_prefetchable_memory, sys->mem_offset);
0149     pci_add_resource_offset(&sys->resources,
0150                 &pci_prefetchable_memory, sys->mem_offset);
0151
0152     return 1;
0153 }
0154
0155 int __init pci_nanoengine_setup(int nr, struct pci_sys_data *sys)
0156 {
0157     int ret = 0;
0158
0159     pcibios_min_io = 0;
0160     pcibios_min_mem = 0;
0161
0162     if (nr == 0) {
0163         sys->mem_offset = NANO_PCI_MEM_RW_PHYS;
0164         sys->io_offset = 0x400;
0165         ret = pci_nanoengine_setup_resources(sys);
0166         /* Enable alternate memory bus master mode, see
0167          * "Intel StrongARM SA1110 Developer's Manual",
0168          * section 10.8, "Alternate Memory Bus Master Mode". */
0169         GPDR = (GPDR & ~GPIO_MBREQ) | GPIO_MBGNT;
0170         GAFR |= GPIO_MBGNT | GPIO_MBREQ;
0171         TUCR |= TUCR_MBGPIO;
0172     }
0173
0174     return ret;
0175 }
0176
0177 static struct hw_pci nanoengine_pci __initdata = {
0178     .map_irq        = pci_nanoengine_map_irq,
0179     .nr_controllers     = 1,
0180     .ops            = &pci_nano_ops,
0181     .setup          = pci_nanoengine_setup,
0182 };
0183
0184 static int __init nanoengine_pci_init(void)
0185 {
0186     if (machine_is_nanoengine())
0187         pci_common_init(&nanoengine_pci);
0188     return 0;
0189 }
0190
0191 subsys_initcall(nanoengine_pci_init);