arm/mach-sa1100/nanoengine.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * linux/arch/arm/mach-sa1100/nanoengine.c
0004  *
0005  * Bright Star Engineering's nanoEngine board init code.
0006  *
0007  * Copyright (C) 2010 Marcelo Roberto Jimenez <mroberto@cpti.cetuc.puc-rio.br>
0008  */
0009
0010 #include <linux/init.h>
0011 #include <linux/gpio/machine.h>
0012 #include <linux/kernel.h>
0013 #include <linux/platform_data/sa11x0-serial.h>
0014 #include <linux/mtd/mtd.h>
0015 #include <linux/mtd/partitions.h>
0016 #include <linux/root_dev.h>
0017
0018 #include <asm/mach-types.h>
0019 #include <asm/setup.h>
0020 #include <asm/page.h>
0021
0022 #include <asm/mach/arch.h>
0023 #include <asm/mach/flash.h>
0024 #include <asm/mach/map.h>
0025
0026 #include <mach/hardware.h>
0027 #include <mach/nanoengine.h>
0028 #include <mach/irqs.h>
0029
0030 #include "generic.h"
0031
0032 /* Flash bank 0 */
0033 static struct mtd_partition nanoengine_partitions[] = {
0034     {
0035         .name   = "nanoEngine boot firmware and parameter table",
0036         .size       = 0x00010000,  /* 32K */
0037         .offset     = 0,
0038         .mask_flags = MTD_WRITEABLE,
0039     }, {
0040         .name       = "kernel/initrd reserved",
0041         .size       = 0x002f0000,
0042         .offset     = 0x00010000,
0043         .mask_flags = MTD_WRITEABLE,
0044     }, {
0045         .name       = "experimental filesystem allocation",
0046         .size       = 0x00100000,
0047         .offset     = 0x00300000,
0048         .mask_flags = MTD_WRITEABLE,
0049     }
0050 };
0051
0052 static struct flash_platform_data nanoengine_flash_data = {
0053     .map_name   = "jedec_probe",
0054     .parts      = nanoengine_partitions,
0055     .nr_parts   = ARRAY_SIZE(nanoengine_partitions),
0056 };
0057
0058 static struct resource nanoengine_flash_resources[] = {
0059     DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_32M),
0060     DEFINE_RES_MEM(SA1100_CS1_PHYS, SZ_32M),
0061 };
0062
0063 static struct map_desc nanoengine_io_desc[] __initdata = {
0064     {
0065         /* System Registers */
0066         .virtual    = 0xf0000000,
0067         .pfn        = __phys_to_pfn(0x10000000),
0068         .length     = 0x00100000,
0069         .type       = MT_DEVICE
0070     }, {
0071         /* Internal PCI Memory Read/Write */
0072         .virtual    = NANO_PCI_MEM_RW_VIRT,
0073         .pfn        = __phys_to_pfn(NANO_PCI_MEM_RW_PHYS),
0074         .length     = NANO_PCI_MEM_RW_SIZE,
0075         .type       = MT_DEVICE
0076     }, {
0077         /* Internal PCI Config Space */
0078         .virtual    = NANO_PCI_CONFIG_SPACE_VIRT,
0079         .pfn        = __phys_to_pfn(NANO_PCI_CONFIG_SPACE_PHYS),
0080         .length     = NANO_PCI_CONFIG_SPACE_SIZE,
0081         .type       = MT_DEVICE
0082     }
0083 };
0084
0085 static void __init nanoengine_map_io(void)
0086 {
0087     sa1100_map_io();
0088     iotable_init(nanoengine_io_desc, ARRAY_SIZE(nanoengine_io_desc));
0089
0090     sa1100_register_uart(0, 1);
0091     sa1100_register_uart(1, 2);
0092     sa1100_register_uart(2, 3);
0093     Ser1SDCR0 |= SDCR0_UART;
0094     /* disable IRDA -- UART2 is used as a normal serial port */
0095     Ser2UTCR4 = 0;
0096     Ser2HSCR0 = 0;
0097 }
0098
0099 static struct gpiod_lookup_table nanoengine_pcmcia0_gpio_table = {
0100     .dev_id = "sa11x0-pcmcia.0",
0101     .table = {
0102         GPIO_LOOKUP("gpio", 11, "ready", GPIO_ACTIVE_HIGH),
0103         GPIO_LOOKUP("gpio", 13, "detect", GPIO_ACTIVE_LOW),
0104         GPIO_LOOKUP("gpio", 15, "reset", GPIO_ACTIVE_HIGH),
0105         { },
0106     },
0107 };
0108
0109 static struct gpiod_lookup_table nanoengine_pcmcia1_gpio_table = {
0110     .dev_id = "sa11x0-pcmcia.1",
0111     .table = {
0112         GPIO_LOOKUP("gpio", 12, "ready", GPIO_ACTIVE_HIGH),
0113         GPIO_LOOKUP("gpio", 14, "detect", GPIO_ACTIVE_LOW),
0114         GPIO_LOOKUP("gpio", 16, "reset", GPIO_ACTIVE_HIGH),
0115         { },
0116     },
0117 };
0118
0119 static void __init nanoengine_init(void)
0120 {
0121     sa11x0_register_pcmcia(0, &nanoengine_pcmcia0_gpio_table);
0122     sa11x0_register_pcmcia(1, &nanoengine_pcmcia1_gpio_table);
0123     sa11x0_register_mtd(&nanoengine_flash_data, nanoengine_flash_resources,
0124         ARRAY_SIZE(nanoengine_flash_resources));
0125 }
0126
0127 MACHINE_START(NANOENGINE, "BSE nanoEngine")
0128     .atag_offset    = 0x100,
0129     .map_io     = nanoengine_map_io,
0130     .nr_irqs    = SA1100_NR_IRQS,
0131     .init_irq   = sa1100_init_irq,
0132     .init_time  = sa1100_timer_init,
0133     .init_machine   = nanoengine_init,
0134     .init_late  = sa11x0_init_late,
0135     .restart    = sa11x0_restart,
0136 MACHINE_END