arm/mach-sa1100/generic.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * linux/arch/arm/mach-sa1100/generic.c
0004  *
0005  * Author: Nicolas Pitre
0006  *
0007  * Code common to all SA11x0 machines.
0008  */
0009 #include <linux/gpio.h>
0010 #include <linux/gpio/machine.h>
0011 #include <linux/module.h>
0012 #include <linux/kernel.h>
0013 #include <linux/init.h>
0014 #include <linux/delay.h>
0015 #include <linux/dma-mapping.h>
0016 #include <linux/pm.h>
0017 #include <linux/cpufreq.h>
0018 #include <linux/ioport.h>
0019 #include <linux/platform_device.h>
0020 #include <linux/reboot.h>
0021 #include <linux/regulator/fixed.h>
0022 #include <linux/regulator/machine.h>
0023 #include <linux/irqchip/irq-sa11x0.h>
0024
0025 #include <video/sa1100fb.h>
0026
0027 #include <soc/sa1100/pwer.h>
0028
0029 #include <asm/div64.h>
0030 #include <asm/mach/map.h>
0031 #include <asm/mach/flash.h>
0032 #include <asm/irq.h>
0033 #include <asm/system_misc.h>
0034
0035 #include <mach/hardware.h>
0036 #include <mach/irqs.h>
0037 #include <mach/reset.h>
0038
0039 #include "generic.h"
0040 #include <clocksource/pxa.h>
0041
0042 #define NR_FREQS    16
0043
0044 /*
0045  * This table is setup for a 3.6864MHz Crystal.
0046  */
0047 struct cpufreq_frequency_table sa11x0_freq_table[NR_FREQS+1] = {
0048     { .frequency = 59000,   /*  59.0 MHz */},
0049     { .frequency = 73700,   /*  73.7 MHz */},
0050     { .frequency = 88500,   /*  88.5 MHz */},
0051     { .frequency = 103200,  /* 103.2 MHz */},
0052     { .frequency = 118000,  /* 118.0 MHz */},
0053     { .frequency = 132700,  /* 132.7 MHz */},
0054     { .frequency = 147500,  /* 147.5 MHz */},
0055     { .frequency = 162200,  /* 162.2 MHz */},
0056     { .frequency = 176900,  /* 176.9 MHz */},
0057     { .frequency = 191700,  /* 191.7 MHz */},
0058     { .frequency = 206400,  /* 206.4 MHz */},
0059     { .frequency = 221200,  /* 221.2 MHz */},
0060     { .frequency = 235900,  /* 235.9 MHz */},
0061     { .frequency = 250700,  /* 250.7 MHz */},
0062     { .frequency = 265400,  /* 265.4 MHz */},
0063     { .frequency = 280200,  /* 280.2 MHz */},
0064     { .frequency = CPUFREQ_TABLE_END, },
0065 };
0066
0067 unsigned int sa11x0_getspeed(unsigned int cpu)
0068 {
0069     if (cpu)
0070         return 0;
0071     return sa11x0_freq_table[PPCR & 0xf].frequency;
0072 }
0073
0074 /*
0075  * Default power-off for SA1100
0076  */
0077 static void sa1100_power_off(void)
0078 {
0079     mdelay(100);
0080     local_irq_disable();
0081     /* disable internal oscillator, float CS lines */
0082     PCFR = (PCFR_OPDE | PCFR_FP | PCFR_FS);
0083     /* enable wake-up on GPIO0 (Assabet...) */
0084     PWER = GFER = GRER = 1;
0085     /*
0086      * set scratchpad to zero, just in case it is used as a
0087      * restart address by the bootloader.
0088      */
0089     PSPR = 0;
0090     /* enter sleep mode */
0091     PMCR = PMCR_SF;
0092 }
0093
0094 void sa11x0_restart(enum reboot_mode mode, const char *cmd)
0095 {
0096     clear_reset_status(RESET_STATUS_ALL);
0097
0098     if (mode == REBOOT_SOFT) {
0099         /* Jump into ROM at address 0 */
0100         soft_restart(0);
0101     } else {
0102         /* Use on-chip reset capability */
0103         RSRR = RSRR_SWR;
0104     }
0105 }
0106
0107 static void sa11x0_register_device(struct platform_device *dev, void *data)
0108 {
0109     int err;
0110     dev->dev.platform_data = data;
0111     err = platform_device_register(dev);
0112     if (err)
0113         printk(KERN_ERR "Unable to register device %s: %d\n",
0114             dev->name, err);
0115 }
0116
0117
0118 static struct resource sa11x0udc_resources[] = {
0119     [0] = DEFINE_RES_MEM(__PREG(Ser0UDCCR), SZ_64K),
0120     [1] = DEFINE_RES_IRQ(IRQ_Ser0UDC),
0121 };
0122
0123 static u64 sa11x0udc_dma_mask = 0xffffffffUL;
0124
0125 static struct platform_device sa11x0udc_device = {
0126     .name       = "sa11x0-udc",
0127     .id     = -1,
0128     .dev        = {
0129         .dma_mask = &sa11x0udc_dma_mask,
0130         .coherent_dma_mask = 0xffffffff,
0131     },
0132     .num_resources  = ARRAY_SIZE(sa11x0udc_resources),
0133     .resource   = sa11x0udc_resources,
0134 };
0135
0136 static struct resource sa11x0uart1_resources[] = {
0137     [0] = DEFINE_RES_MEM(__PREG(Ser1UTCR0), SZ_64K),
0138     [1] = DEFINE_RES_IRQ(IRQ_Ser1UART),
0139 };
0140
0141 static struct platform_device sa11x0uart1_device = {
0142     .name       = "sa11x0-uart",
0143     .id     = 1,
0144     .num_resources  = ARRAY_SIZE(sa11x0uart1_resources),
0145     .resource   = sa11x0uart1_resources,
0146 };
0147
0148 static struct resource sa11x0uart3_resources[] = {
0149     [0] = DEFINE_RES_MEM(__PREG(Ser3UTCR0), SZ_64K),
0150     [1] = DEFINE_RES_IRQ(IRQ_Ser3UART),
0151 };
0152
0153 static struct platform_device sa11x0uart3_device = {
0154     .name       = "sa11x0-uart",
0155     .id     = 3,
0156     .num_resources  = ARRAY_SIZE(sa11x0uart3_resources),
0157     .resource   = sa11x0uart3_resources,
0158 };
0159
0160 static struct resource sa11x0mcp_resources[] = {
0161     [0] = DEFINE_RES_MEM(__PREG(Ser4MCCR0), SZ_64K),
0162     [1] = DEFINE_RES_MEM(__PREG(Ser4MCCR1), 4),
0163     [2] = DEFINE_RES_IRQ(IRQ_Ser4MCP),
0164 };
0165
0166 static u64 sa11x0mcp_dma_mask = 0xffffffffUL;
0167
0168 static struct platform_device sa11x0mcp_device = {
0169     .name       = "sa11x0-mcp",
0170     .id     = -1,
0171     .dev = {
0172         .dma_mask = &sa11x0mcp_dma_mask,
0173         .coherent_dma_mask = 0xffffffff,
0174     },
0175     .num_resources  = ARRAY_SIZE(sa11x0mcp_resources),
0176     .resource   = sa11x0mcp_resources,
0177 };
0178
0179 void __init sa11x0_ppc_configure_mcp(void)
0180 {
0181     /* Setup the PPC unit for the MCP */
0182     PPDR &= ~PPC_RXD4;
0183     PPDR |= PPC_TXD4 | PPC_SCLK | PPC_SFRM;
0184     PSDR |= PPC_RXD4;
0185     PSDR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM);
0186     PPSR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM);
0187 }
0188
0189 void sa11x0_register_mcp(struct mcp_plat_data *data)
0190 {
0191     sa11x0_register_device(&sa11x0mcp_device, data);
0192 }
0193
0194 static struct resource sa11x0ssp_resources[] = {
0195     [0] = DEFINE_RES_MEM(0x80070000, SZ_64K),
0196     [1] = DEFINE_RES_IRQ(IRQ_Ser4SSP),
0197 };
0198
0199 static u64 sa11x0ssp_dma_mask = 0xffffffffUL;
0200
0201 static struct platform_device sa11x0ssp_device = {
0202     .name       = "sa11x0-ssp",
0203     .id     = -1,
0204     .dev = {
0205         .dma_mask = &sa11x0ssp_dma_mask,
0206         .coherent_dma_mask = 0xffffffff,
0207     },
0208     .num_resources  = ARRAY_SIZE(sa11x0ssp_resources),
0209     .resource   = sa11x0ssp_resources,
0210 };
0211
0212 static struct resource sa11x0fb_resources[] = {
0213     [0] = DEFINE_RES_MEM(0xb0100000, SZ_64K),
0214     [1] = DEFINE_RES_IRQ(IRQ_LCD),
0215 };
0216
0217 static struct platform_device sa11x0fb_device = {
0218     .name       = "sa11x0-fb",
0219     .id     = -1,
0220     .dev = {
0221         .coherent_dma_mask = 0xffffffff,
0222     },
0223     .num_resources  = ARRAY_SIZE(sa11x0fb_resources),
0224     .resource   = sa11x0fb_resources,
0225 };
0226
0227 void sa11x0_register_lcd(struct sa1100fb_mach_info *inf)
0228 {
0229     sa11x0_register_device(&sa11x0fb_device, inf);
0230 }
0231
0232 void sa11x0_register_pcmcia(int socket, struct gpiod_lookup_table *table)
0233 {
0234     if (table)
0235         gpiod_add_lookup_table(table);
0236     platform_device_register_simple("sa11x0-pcmcia", socket, NULL, 0);
0237 }
0238
0239 static struct platform_device sa11x0mtd_device = {
0240     .name       = "sa1100-mtd",
0241     .id     = -1,
0242 };
0243
0244 void sa11x0_register_mtd(struct flash_platform_data *flash,
0245              struct resource *res, int nr)
0246 {
0247     flash->name = "sa1100";
0248     sa11x0mtd_device.resource = res;
0249     sa11x0mtd_device.num_resources = nr;
0250     sa11x0_register_device(&sa11x0mtd_device, flash);
0251 }
0252
0253 static struct resource sa11x0ir_resources[] = {
0254     DEFINE_RES_MEM(__PREG(Ser2UTCR0), 0x24),
0255     DEFINE_RES_MEM(__PREG(Ser2HSCR0), 0x1c),
0256     DEFINE_RES_MEM(__PREG(Ser2HSCR2), 0x04),
0257     DEFINE_RES_IRQ(IRQ_Ser2ICP),
0258 };
0259
0260 static struct platform_device sa11x0ir_device = {
0261     .name       = "sa11x0-ir",
0262     .id     = -1,
0263     .num_resources  = ARRAY_SIZE(sa11x0ir_resources),
0264     .resource   = sa11x0ir_resources,
0265 };
0266
0267 void sa11x0_register_irda(struct irda_platform_data *irda)
0268 {
0269     sa11x0_register_device(&sa11x0ir_device, irda);
0270 }
0271
0272 static struct resource sa1100_rtc_resources[] = {
0273     DEFINE_RES_MEM(0x90010000, 0x40),
0274     DEFINE_RES_IRQ_NAMED(IRQ_RTC1Hz, "rtc 1Hz"),
0275     DEFINE_RES_IRQ_NAMED(IRQ_RTCAlrm, "rtc alarm"),
0276 };
0277
0278 static struct platform_device sa11x0rtc_device = {
0279     .name       = "sa1100-rtc",
0280     .id     = -1,
0281     .num_resources  = ARRAY_SIZE(sa1100_rtc_resources),
0282     .resource   = sa1100_rtc_resources,
0283 };
0284
0285 static struct resource sa11x0dma_resources[] = {
0286     DEFINE_RES_MEM(DMA_PHYS, DMA_SIZE),
0287     DEFINE_RES_IRQ(IRQ_DMA0),
0288     DEFINE_RES_IRQ(IRQ_DMA1),
0289     DEFINE_RES_IRQ(IRQ_DMA2),
0290     DEFINE_RES_IRQ(IRQ_DMA3),
0291     DEFINE_RES_IRQ(IRQ_DMA4),
0292     DEFINE_RES_IRQ(IRQ_DMA5),
0293 };
0294
0295 static u64 sa11x0dma_dma_mask = DMA_BIT_MASK(32);
0296
0297 static struct platform_device sa11x0dma_device = {
0298     .name       = "sa11x0-dma",
0299     .id     = -1,
0300     .dev = {
0301         .dma_mask = &sa11x0dma_dma_mask,
0302         .coherent_dma_mask = 0xffffffff,
0303     },
0304     .num_resources  = ARRAY_SIZE(sa11x0dma_resources),
0305     .resource   = sa11x0dma_resources,
0306 };
0307
0308 static struct platform_device *sa11x0_devices[] __initdata = {
0309     &sa11x0udc_device,
0310     &sa11x0uart1_device,
0311     &sa11x0uart3_device,
0312     &sa11x0ssp_device,
0313     &sa11x0rtc_device,
0314     &sa11x0dma_device,
0315 };
0316
0317 static int __init sa1100_init(void)
0318 {
0319     struct resource wdt_res = DEFINE_RES_MEM(0x90000000, 0x20);
0320     pm_power_off = sa1100_power_off;
0321
0322     regulator_has_full_constraints();
0323
0324     platform_device_register_simple("sa1100_wdt", -1, &wdt_res, 1);
0325
0326     return platform_add_devices(sa11x0_devices, ARRAY_SIZE(sa11x0_devices));
0327 }
0328
0329 arch_initcall(sa1100_init);
0330
0331 void __init sa11x0_init_late(void)
0332 {
0333     sa11x0_pm_init();
0334 }
0335
0336 int __init sa11x0_register_fixed_regulator(int n,
0337     struct fixed_voltage_config *cfg,
0338     struct regulator_consumer_supply *supplies, unsigned num_supplies,
0339     bool uses_gpio)
0340 {
0341     struct regulator_init_data *id;
0342
0343     cfg->init_data = id = kzalloc(sizeof(*cfg->init_data), GFP_KERNEL);
0344     if (!cfg->init_data)
0345         return -ENOMEM;
0346
0347     if (!uses_gpio)
0348         id->constraints.always_on = 1;
0349     id->constraints.name = cfg->supply_name;
0350     id->constraints.min_uV = cfg->microvolts;
0351     id->constraints.max_uV = cfg->microvolts;
0352     id->constraints.valid_modes_mask = REGULATOR_MODE_NORMAL;
0353     id->constraints.valid_ops_mask = REGULATOR_CHANGE_STATUS;
0354     id->consumer_supplies = supplies;
0355     id->num_consumer_supplies = num_supplies;
0356
0357     platform_device_register_resndata(NULL, "reg-fixed-voltage", n,
0358                       NULL, 0, cfg, sizeof(*cfg));
0359     return 0;
0360 }
0361
0362 /*
0363  * Common I/O mapping:
0364  *
0365  * Typically, static virtual address mappings are as follow:
0366  *
0367  * 0xf0000000-0xf3ffffff:   miscellaneous stuff (CPLDs, etc.)
0368  * 0xf4000000-0xf4ffffff:   SA-1111
0369  * 0xf5000000-0xf5ffffff:   reserved (used by cache flushing area)
0370  * 0xf6000000-0xfffeffff:   reserved (internal SA1100 IO defined above)
0371  * 0xffff0000-0xffff0fff:   SA1100 exception vectors
0372  * 0xffff2000-0xffff2fff:   Minicache copy_user_page area
0373  *
0374  * Below 0xe8000000 is reserved for vm allocation.
0375  *
0376  * The machine specific code must provide the extra mapping beside the
0377  * default mapping provided here.
0378  */
0379
0380 static struct map_desc standard_io_desc[] __initdata = {
0381     {   /* PCM */
0382         .virtual    =  0xf8000000,
0383         .pfn        = __phys_to_pfn(0x80000000),
0384         .length     = 0x00100000,
0385         .type       = MT_DEVICE
0386     }, {    /* SCM */
0387         .virtual    =  0xfa000000,
0388         .pfn        = __phys_to_pfn(0x90000000),
0389         .length     = 0x00100000,
0390         .type       = MT_DEVICE
0391     }, {    /* MER */
0392         .virtual    =  0xfc000000,
0393         .pfn        = __phys_to_pfn(0xa0000000),
0394         .length     = 0x00100000,
0395         .type       = MT_DEVICE
0396     }, {    /* LCD + DMA */
0397         .virtual    =  0xfe000000,
0398         .pfn        = __phys_to_pfn(0xb0000000),
0399         .length     = 0x00200000,
0400         .type       = MT_DEVICE
0401     },
0402 };
0403
0404 void __init sa1100_map_io(void)
0405 {
0406     iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc));
0407 }
0408
0409 void __init sa1100_timer_init(void)
0410 {
0411     pxa_timer_nodt_init(IRQ_OST0, io_p2v(0x90000000));
0412 }
0413
0414 static struct resource irq_resource =
0415     DEFINE_RES_MEM_NAMED(0x90050000, SZ_64K, "irqs");
0416
0417 void __init sa1100_init_irq(void)
0418 {
0419     request_resource(&iomem_resource, &irq_resource);
0420
0421     sa11x0_init_irq_nodt(IRQ_GPIO0_SC, irq_resource.start);
0422
0423     sa1100_init_gpio();
0424     sa11xx_clk_init();
0425 }
0426
0427 /*
0428  * Disable the memory bus request/grant signals on the SA1110 to
0429  * ensure that we don't receive spurious memory requests.  We set
0430  * the MBGNT signal false to ensure the SA1111 doesn't own the
0431  * SDRAM bus.
0432  */
0433 void sa1110_mb_disable(void)
0434 {
0435     unsigned long flags;
0436
0437     local_irq_save(flags);
0438
0439     PGSR &= ~GPIO_MBGNT;
0440     GPCR = GPIO_MBGNT;
0441     GPDR = (GPDR & ~GPIO_MBREQ) | GPIO_MBGNT;
0442
0443     GAFR &= ~(GPIO_MBGNT | GPIO_MBREQ);
0444
0445     local_irq_restore(flags);
0446 }
0447
0448 /*
0449  * If the system is going to use the SA-1111 DMA engines, set up
0450  * the memory bus request/grant pins.
0451  */
0452 void sa1110_mb_enable(void)
0453 {
0454     unsigned long flags;
0455
0456     local_irq_save(flags);
0457
0458     PGSR &= ~GPIO_MBGNT;
0459     GPCR = GPIO_MBGNT;
0460     GPDR = (GPDR & ~GPIO_MBREQ) | GPIO_MBGNT;
0461
0462     GAFR |= (GPIO_MBGNT | GPIO_MBREQ);
0463     TUCR |= TUCR_MR;
0464
0465     local_irq_restore(flags);
0466 }
0467
0468 int sa11x0_gpio_set_wake(unsigned int gpio, unsigned int on)
0469 {
0470     if (on)
0471         PWER |= BIT(gpio);
0472     else
0473         PWER &= ~BIT(gpio);
0474
0475     return 0;
0476 }
0477
0478 int sa11x0_sc_set_wake(unsigned int irq, unsigned int on)
0479 {
0480     if (BIT(irq) != IC_RTCAlrm)
0481         return -EINVAL;
0482
0483     if (on)
0484         PWER |= PWER_RTC;
0485     else
0486         PWER &= ~PWER_RTC;
0487
0488     return 0;
0489 }