arm/mach-sa1100/cerf.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * linux/arch/arm/mach-sa1100/cerf.c
0004  *
0005  * Apr-2003 : Removed some old PDA crud [FB]
0006  * Oct-2003 : Added uart2 resource [FB]
0007  * Jan-2004 : Removed io map for flash [FB]
0008  */
0009
0010 #include <linux/init.h>
0011 #include <linux/gpio/machine.h>
0012 #include <linux/kernel.h>
0013 #include <linux/tty.h>
0014 #include <linux/platform_data/sa11x0-serial.h>
0015 #include <linux/platform_device.h>
0016 #include <linux/irq.h>
0017 #include <linux/mtd/mtd.h>
0018 #include <linux/mtd/partitions.h>
0019 #include <linux/gpio.h>
0020 #include <linux/leds.h>
0021
0022 #include <mach/hardware.h>
0023 #include <asm/setup.h>
0024
0025 #include <asm/mach-types.h>
0026 #include <asm/mach/arch.h>
0027 #include <asm/mach/flash.h>
0028 #include <asm/mach/map.h>
0029
0030 #include <mach/cerf.h>
0031 #include <linux/platform_data/mfd-mcp-sa11x0.h>
0032 #include <mach/irqs.h>
0033 #include "generic.h"
0034
0035 static struct resource cerfuart2_resources[] = {
0036     [0] = DEFINE_RES_MEM(0x80030000, SZ_64K),
0037 };
0038
0039 static struct platform_device cerfuart2_device = {
0040     .name       = "sa11x0-uart",
0041     .id     = 2,
0042     .num_resources  = ARRAY_SIZE(cerfuart2_resources),
0043     .resource   = cerfuart2_resources,
0044 };
0045
0046 /* Compact Flash */
0047 static struct gpiod_lookup_table cerf_cf_gpio_table = {
0048     .dev_id = "sa11x0-pcmcia.1",
0049     .table = {
0050         GPIO_LOOKUP("gpio", 19, "bvd2", GPIO_ACTIVE_HIGH),
0051         GPIO_LOOKUP("gpio", 20, "bvd1", GPIO_ACTIVE_HIGH),
0052         GPIO_LOOKUP("gpio", 21, "reset", GPIO_ACTIVE_HIGH),
0053         GPIO_LOOKUP("gpio", 22, "ready", GPIO_ACTIVE_HIGH),
0054         GPIO_LOOKUP("gpio", 23, "detect", GPIO_ACTIVE_LOW),
0055         { },
0056     },
0057 };
0058
0059 /* LEDs */
0060 struct gpio_led cerf_gpio_leds[] = {
0061     {
0062         .name           = "cerf:d0",
0063         .default_trigger    = "heartbeat",
0064         .gpio           = 0,
0065     },
0066     {
0067         .name           = "cerf:d1",
0068         .default_trigger    = "cpu0",
0069         .gpio           = 1,
0070     },
0071     {
0072         .name           = "cerf:d2",
0073         .default_trigger    = "default-on",
0074         .gpio           = 2,
0075     },
0076     {
0077         .name           = "cerf:d3",
0078         .default_trigger    = "default-on",
0079         .gpio           = 3,
0080     },
0081
0082 };
0083
0084 static struct gpio_led_platform_data cerf_gpio_led_info = {
0085     .leds       = cerf_gpio_leds,
0086     .num_leds   = ARRAY_SIZE(cerf_gpio_leds),
0087 };
0088
0089 static struct platform_device *cerf_devices[] __initdata = {
0090     &cerfuart2_device,
0091 };
0092
0093 #ifdef CONFIG_SA1100_CERF_FLASH_32MB
0094 #  define CERF_FLASH_SIZE   0x02000000
0095 #elif defined CONFIG_SA1100_CERF_FLASH_16MB
0096 #  define CERF_FLASH_SIZE   0x01000000
0097 #elif defined CONFIG_SA1100_CERF_FLASH_8MB
0098 #  define CERF_FLASH_SIZE   0x00800000
0099 #else
0100 #  error "Undefined flash size for CERF"
0101 #endif
0102
0103 static struct mtd_partition cerf_partitions[] = {
0104     {
0105         .name       = "Bootloader",
0106         .size       = 0x00020000,
0107         .offset     = 0x00000000,
0108     }, {
0109         .name       = "Params",
0110         .size       = 0x00040000,
0111         .offset     = 0x00020000,
0112     }, {
0113         .name       = "Kernel",
0114         .size       = 0x00100000,
0115         .offset     = 0x00060000,
0116     }, {
0117         .name       = "Filesystem",
0118         .size       = CERF_FLASH_SIZE-0x00160000,
0119         .offset     = 0x00160000,
0120     }
0121 };
0122
0123 static struct flash_platform_data cerf_flash_data = {
0124     .map_name   = "cfi_probe",
0125     .parts      = cerf_partitions,
0126     .nr_parts   = ARRAY_SIZE(cerf_partitions),
0127 };
0128
0129 static struct resource cerf_flash_resource =
0130     DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_32M);
0131
0132 static void __init cerf_init_irq(void)
0133 {
0134     sa1100_init_irq();
0135     irq_set_irq_type(CERF_ETH_IRQ, IRQ_TYPE_EDGE_RISING);
0136 }
0137
0138 static struct map_desc cerf_io_desc[] __initdata = {
0139     {   /* Crystal Ethernet Chip */
0140         .virtual    =  0xf0000000,
0141         .pfn        = __phys_to_pfn(0x08000000),
0142         .length     = 0x00100000,
0143         .type       = MT_DEVICE
0144     }
0145 };
0146
0147 static void __init cerf_map_io(void)
0148 {
0149     sa1100_map_io();
0150     iotable_init(cerf_io_desc, ARRAY_SIZE(cerf_io_desc));
0151
0152     sa1100_register_uart(0, 3);
0153     sa1100_register_uart(1, 2); /* disable this and the uart2 device for sa1100_fir */
0154     sa1100_register_uart(2, 1);
0155 }
0156
0157 static struct mcp_plat_data cerf_mcp_data = {
0158     .mccr0      = MCCR0_ADM,
0159     .sclk_rate  = 11981000,
0160 };
0161
0162 static void __init cerf_init(void)
0163 {
0164     sa11x0_ppc_configure_mcp();
0165     platform_add_devices(cerf_devices, ARRAY_SIZE(cerf_devices));
0166     gpio_led_register_device(-1, &cerf_gpio_led_info);
0167     sa11x0_register_mtd(&cerf_flash_data, &cerf_flash_resource, 1);
0168     sa11x0_register_mcp(&cerf_mcp_data);
0169     sa11x0_register_pcmcia(1, &cerf_cf_gpio_table);
0170 }
0171
0172 MACHINE_START(CERF, "Intrinsyc CerfBoard/CerfCube")
0173     /* Maintainer: support@intrinsyc.com */
0174     .map_io     = cerf_map_io,
0175     .nr_irqs    = SA1100_NR_IRQS,
0176     .init_irq   = cerf_init_irq,
0177     .init_time  = sa1100_timer_init,
0178     .init_machine   = cerf_init,
0179     .init_late  = sa11x0_init_late,
0180     .restart    = sa11x0_restart,
0181 MACHINE_END