arm/mach-s3c/vr1000.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright (c) 2003 Simtec Electronics
0004  *  Ben Dooks <ben@simtec.co.uk>
0005  *
0006  * VR1000 - CPLD control constants
0007  * Machine VR1000 - IRQ Number definitions
0008  * Machine VR1000 - Memory map definitions
0009  */
0010
0011 #ifndef __MACH_S3C24XX_VR1000_H
0012 #define __MACH_S3C24XX_VR1000_H __FILE__
0013
0014 #define VR1000_CPLD_CTRL2_RAMWEN    (0x04)  /* SRAM Write Enable */
0015
0016 /* irq numbers to onboard peripherals */
0017
0018 #define VR1000_IRQ_USBOC        IRQ_EINT19
0019 #define VR1000_IRQ_IDE0         IRQ_EINT16
0020 #define VR1000_IRQ_IDE1         IRQ_EINT17
0021 #define VR1000_IRQ_SERIAL       IRQ_EINT12
0022 #define VR1000_IRQ_DM9000A      IRQ_EINT10
0023 #define VR1000_IRQ_DM9000N      IRQ_EINT9
0024 #define VR1000_IRQ_SMALERT      IRQ_EINT8
0025
0026 /* map */
0027
0028 #define VR1000_IOADDR(x)        (S3C2410_ADDR((x) + 0x01300000))
0029
0030 /* we put the CPLD registers next, to get them out of the way */
0031
0032 #define VR1000_VA_CTRL1         VR1000_IOADDR(0x00000000) /* 0x01300000 */
0033 #define VR1000_PA_CTRL1         (S3C2410_CS5 | 0x7800000)
0034
0035 #define VR1000_VA_CTRL2         VR1000_IOADDR(0x00100000) /* 0x01400000 */
0036 #define VR1000_PA_CTRL2         (S3C2410_CS1 | 0x6000000)
0037
0038 #define VR1000_VA_CTRL3         VR1000_IOADDR(0x00200000) /* 0x01500000 */
0039 #define VR1000_PA_CTRL3         (S3C2410_CS1 | 0x6800000)
0040
0041 #define VR1000_VA_CTRL4         VR1000_IOADDR(0x00300000) /* 0x01600000 */
0042 #define VR1000_PA_CTRL4         (S3C2410_CS1 | 0x7000000)
0043
0044 /* next, we have the PC104 ISA interrupt registers */
0045
0046 #define VR1000_PA_PC104_IRQREQ      (S3C2410_CS5 | 0x6000000) /* 0x01700000 */
0047 #define VR1000_VA_PC104_IRQREQ      VR1000_IOADDR(0x00400000)
0048
0049 #define VR1000_PA_PC104_IRQRAW      (S3C2410_CS5 | 0x6800000) /* 0x01800000 */
0050 #define VR1000_VA_PC104_IRQRAW      VR1000_IOADDR(0x00500000)
0051
0052 #define VR1000_PA_PC104_IRQMASK     (S3C2410_CS5 | 0x7000000) /* 0x01900000 */
0053 #define VR1000_VA_PC104_IRQMASK     VR1000_IOADDR(0x00600000)
0054
0055 /*
0056  * 0xE0000000 contains the IO space that is split by speed and
0057  * whether the access is for 8 or 16bit IO... this ensures that
0058  * the correct access is made
0059  *
0060  * 0x10000000 of space, partitioned as so:
0061  *
0062  * 0x00000000 to 0x04000000  8bit,  slow
0063  * 0x04000000 to 0x08000000  16bit, slow
0064  * 0x08000000 to 0x0C000000  16bit, net
0065  * 0x0C000000 to 0x10000000  16bit, fast
0066  *
0067  * each of these spaces has the following in:
0068  *
0069  * 0x02000000 to 0x02100000 1MB  IDE primary channel
0070  * 0x02100000 to 0x02200000 1MB  IDE primary channel aux
0071  * 0x02200000 to 0x02400000 1MB  IDE secondary channel
0072  * 0x02300000 to 0x02400000 1MB  IDE secondary channel aux
0073  * 0x02500000 to 0x02600000 1MB  Davicom DM9000 ethernet controllers
0074  * 0x02600000 to 0x02700000 1MB
0075  *
0076  * the phyiscal layout of the zones are:
0077  *  nGCS2 - 8bit, slow
0078  *  nGCS3 - 16bit, slow
0079  *  nGCS4 - 16bit, net
0080  *  nGCS5 - 16bit, fast
0081  */
0082
0083 #define VR1000_VA_MULTISPACE    (0xE0000000)
0084
0085 #define VR1000_VA_ISAIO     (VR1000_VA_MULTISPACE + 0x00000000)
0086 #define VR1000_VA_ISAMEM    (VR1000_VA_MULTISPACE + 0x01000000)
0087 #define VR1000_VA_IDEPRI    (VR1000_VA_MULTISPACE + 0x02000000)
0088 #define VR1000_VA_IDEPRIAUX (VR1000_VA_MULTISPACE + 0x02100000)
0089 #define VR1000_VA_IDESEC    (VR1000_VA_MULTISPACE + 0x02200000)
0090 #define VR1000_VA_IDESECAUX (VR1000_VA_MULTISPACE + 0x02300000)
0091 #define VR1000_VA_ASIXNET   (VR1000_VA_MULTISPACE + 0x02400000)
0092 #define VR1000_VA_DM9000    (VR1000_VA_MULTISPACE + 0x02500000)
0093 #define VR1000_VA_SUPERIO   (VR1000_VA_MULTISPACE + 0x02600000)
0094
0095 /* physical offset addresses for the peripherals */
0096
0097 #define VR1000_PA_IDEPRI    (0x02000000)
0098 #define VR1000_PA_IDEPRIAUX (0x02800000)
0099 #define VR1000_PA_IDESEC    (0x03000000)
0100 #define VR1000_PA_IDESECAUX (0x03800000)
0101 #define VR1000_PA_DM9000    (0x05000000)
0102
0103 #define VR1000_PA_SERIAL    (0x11800000)
0104 #define VR1000_VA_SERIAL    (VR1000_IOADDR(0x00700000))
0105
0106 /* VR1000 ram is in CS1, with A26..A24 = 2_101 */
0107 #define VR1000_PA_SRAM      (S3C2410_CS1 | 0x05000000)
0108
0109 /* some configurations for the peripherals */
0110
0111 #define VR1000_DM9000_CS    VR1000_VAM_CS4
0112
0113 #endif /* __MACH_S3C24XX_VR1000_H */