arm/mach-s3c/setup-ide-s3c64xx.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 //
0003 // Copyright (c) 2010 Samsung Electronics Co., Ltd.
0004 //      http://www.samsung.com/
0005 //
0006 // S3C64XX setup information for IDE
0007
0008 #include <linux/kernel.h>
0009 #include <linux/gpio.h>
0010 #include <linux/io.h>
0011
0012 #include <linux/platform_data/ata-samsung_cf.h>
0013
0014 #include "map.h"
0015 #include "regs-clock.h"
0016 #include "gpio-cfg.h"
0017 #include "gpio-samsung.h"
0018
0019 void s3c64xx_ide_setup_gpio(void)
0020 {
0021     u32 reg;
0022
0023     reg = readl(S3C_MEM_SYS_CFG) & (~0x3f);
0024
0025     /* Independent CF interface, CF chip select configuration */
0026     writel(reg | MEM_SYS_CFG_INDEP_CF |
0027         MEM_SYS_CFG_EBI_FIX_PRI_CFCON, S3C_MEM_SYS_CFG);
0028
0029     s3c_gpio_cfgpin(S3C64XX_GPB(4), S3C_GPIO_SFN(4));
0030
0031     /* Set XhiDATA[15:0] pins as CF Data[15:0] */
0032     s3c_gpio_cfgpin_range(S3C64XX_GPK(0), 16, S3C_GPIO_SFN(5));
0033
0034     /* Set XhiADDR[2:0] pins as CF ADDR[2:0] */
0035     s3c_gpio_cfgpin_range(S3C64XX_GPL(0), 3, S3C_GPIO_SFN(6));
0036
0037     /* Set Xhi ctrl pins as CF ctrl pins(IORDY, IOWR, IORD, CE[0:1]) */
0038     s3c_gpio_cfgpin(S3C64XX_GPM(5), S3C_GPIO_SFN(1));
0039     s3c_gpio_cfgpin_range(S3C64XX_GPM(0), 5, S3C_GPIO_SFN(6));
0040 }