0001
0002
0003
0004
0005
0006
0007
0008
0009
0010
0011
0012
0013
0014 #ifndef __ARCH_ARM_MACH_S3C64XX_COMMON_H
0015 #define __ARCH_ARM_MACH_S3C64XX_COMMON_H
0016
0017 #include <linux/reboot.h>
0018
0019 void s3c64xx_init_irq(u32 vic0, u32 vic1);
0020 void s3c64xx_init_io(struct map_desc *mach_desc, int size);
0021
0022 struct device_node;
0023 void s3c64xx_set_xtal_freq(unsigned long freq);
0024 void s3c64xx_set_xusbxti_freq(unsigned long freq);
0025
0026 #ifdef CONFIG_CPU_S3C6400
0027
0028 extern int s3c6400_init(void);
0029 extern void s3c6400_init_irq(void);
0030 extern void s3c6400_map_io(void);
0031
0032 #else
0033 #define s3c6400_map_io NULL
0034 #define s3c6400_init NULL
0035 #endif
0036
0037 #ifdef CONFIG_CPU_S3C6410
0038
0039 extern int s3c6410_init(void);
0040 extern void s3c6410_init_irq(void);
0041 extern void s3c6410_map_io(void);
0042
0043 #else
0044 #define s3c6410_map_io NULL
0045 #define s3c6410_init NULL
0046 #endif
0047
0048 #ifdef CONFIG_S3C64XX_PL080
0049 extern struct pl08x_platform_data s3c64xx_dma0_plat_data;
0050 extern struct pl08x_platform_data s3c64xx_dma1_plat_data;
0051 #endif
0052
0053
0054 enum s3c64xx_timer_mode {
0055 S3C64XX_PWM0,
0056 S3C64XX_PWM1,
0057 S3C64XX_PWM2,
0058 S3C64XX_PWM3,
0059 S3C64XX_PWM4,
0060 };
0061
0062 extern void __init s3c64xx_set_timer_source(enum s3c64xx_timer_mode event,
0063 enum s3c64xx_timer_mode source);
0064 extern void __init s3c64xx_timer_init(void);
0065
0066 #endif