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0001 // SPDX-License-Identifier: GPL-2.0+
0002 //
0003 // Copyright (c) 2004-2005 Simtec Electronics
0004 //  http://www.simtec.co.uk/products/SWLINUX/
0005 //  Ben Dooks <ben@simtec.co.uk>
0006 //
0007 // Common code for S3C24XX machines
0008 
0009 #include <linux/dma-mapping.h>
0010 #include <linux/init.h>
0011 #include <linux/module.h>
0012 #include <linux/interrupt.h>
0013 #include <linux/ioport.h>
0014 #include <linux/serial_core.h>
0015 #include <linux/serial_s3c.h>
0016 #include <clocksource/samsung_pwm.h>
0017 #include <linux/platform_device.h>
0018 #include <linux/delay.h>
0019 #include <linux/io.h>
0020 #include <linux/platform_data/clk-s3c2410.h>
0021 #include <linux/platform_data/dma-s3c24xx.h>
0022 #include <linux/dmaengine.h>
0023 #include <linux/clk/samsung.h>
0024 
0025 #include "hardware-s3c24xx.h"
0026 #include "map.h"
0027 #include "regs-clock.h"
0028 #include <asm/irq.h>
0029 #include <asm/cacheflush.h>
0030 #include <asm/system_info.h>
0031 #include <asm/system_misc.h>
0032 
0033 #include <asm/mach/arch.h>
0034 #include <asm/mach/map.h>
0035 
0036 #include "regs-gpio.h"
0037 #include "dma-s3c24xx.h"
0038 
0039 #include "cpu.h"
0040 #include "devs.h"
0041 #include "pwm-core.h"
0042 
0043 #include "s3c24xx.h"
0044 
0045 /* table of supported CPUs */
0046 
0047 static const char name_s3c2410[]  = "S3C2410";
0048 static const char name_s3c2412[]  = "S3C2412";
0049 static const char name_s3c2416[]  = "S3C2416/S3C2450";
0050 static const char name_s3c2440[]  = "S3C2440";
0051 static const char name_s3c2442[]  = "S3C2442";
0052 static const char name_s3c2442b[]  = "S3C2442B";
0053 static const char name_s3c2443[]  = "S3C2443";
0054 static const char name_s3c2410a[] = "S3C2410A";
0055 static const char name_s3c2440a[] = "S3C2440A";
0056 
0057 static struct cpu_table cpu_ids[] __initdata = {
0058     {
0059         .idcode     = 0x32410000,
0060         .idmask     = 0xffffffff,
0061         .map_io     = s3c2410_map_io,
0062         .init_uarts = s3c2410_init_uarts,
0063         .init       = s3c2410_init,
0064         .name       = name_s3c2410
0065     },
0066     {
0067         .idcode     = 0x32410002,
0068         .idmask     = 0xffffffff,
0069         .map_io     = s3c2410_map_io,
0070         .init_uarts = s3c2410_init_uarts,
0071         .init       = s3c2410a_init,
0072         .name       = name_s3c2410a
0073     },
0074     {
0075         .idcode     = 0x32440000,
0076         .idmask     = 0xffffffff,
0077         .map_io     = s3c2440_map_io,
0078         .init_uarts = s3c244x_init_uarts,
0079         .init       = s3c2440_init,
0080         .name       = name_s3c2440
0081     },
0082     {
0083         .idcode     = 0x32440001,
0084         .idmask     = 0xffffffff,
0085         .map_io     = s3c2440_map_io,
0086         .init_uarts = s3c244x_init_uarts,
0087         .init       = s3c2440_init,
0088         .name       = name_s3c2440a
0089     },
0090     {
0091         .idcode     = 0x32440aaa,
0092         .idmask     = 0xffffffff,
0093         .map_io     = s3c2442_map_io,
0094         .init_uarts = s3c244x_init_uarts,
0095         .init       = s3c2442_init,
0096         .name       = name_s3c2442
0097     },
0098     {
0099         .idcode     = 0x32440aab,
0100         .idmask     = 0xffffffff,
0101         .map_io     = s3c2442_map_io,
0102         .init_uarts = s3c244x_init_uarts,
0103         .init       = s3c2442_init,
0104         .name       = name_s3c2442b
0105     },
0106     {
0107         .idcode     = 0x32412001,
0108         .idmask     = 0xffffffff,
0109         .map_io     = s3c2412_map_io,
0110         .init_uarts = s3c2412_init_uarts,
0111         .init       = s3c2412_init,
0112         .name       = name_s3c2412,
0113     },
0114     {           /* a newer version of the s3c2412 */
0115         .idcode     = 0x32412003,
0116         .idmask     = 0xffffffff,
0117         .map_io     = s3c2412_map_io,
0118         .init_uarts = s3c2412_init_uarts,
0119         .init       = s3c2412_init,
0120         .name       = name_s3c2412,
0121     },
0122     {           /* a strange version of the s3c2416 */
0123         .idcode     = 0x32450003,
0124         .idmask     = 0xffffffff,
0125         .map_io     = s3c2416_map_io,
0126         .init_uarts = s3c2416_init_uarts,
0127         .init       = s3c2416_init,
0128         .name       = name_s3c2416,
0129     },
0130     {
0131         .idcode     = 0x32443001,
0132         .idmask     = 0xffffffff,
0133         .map_io     = s3c2443_map_io,
0134         .init_uarts = s3c2443_init_uarts,
0135         .init       = s3c2443_init,
0136         .name       = name_s3c2443,
0137     },
0138 };
0139 
0140 /* minimal IO mapping */
0141 
0142 static struct map_desc s3c_iodesc[] __initdata __maybe_unused = {
0143     IODESC_ENT(GPIO),
0144     IODESC_ENT(IRQ),
0145     IODESC_ENT(MEMCTRL),
0146     IODESC_ENT(UART)
0147 };
0148 
0149 /* read cpu identification code */
0150 
0151 static unsigned long s3c24xx_read_idcode_v5(void)
0152 {
0153 #if defined(CONFIG_CPU_S3C2416)
0154     /* s3c2416 is v5, with S3C24XX_GSTATUS1 instead of S3C2412_GSTATUS1 */
0155 
0156     u32 gs = __raw_readl(S3C24XX_GSTATUS1);
0157 
0158     /* test for s3c2416 or similar device */
0159     if ((gs >> 16) == 0x3245)
0160         return gs;
0161 #endif
0162 
0163 #if defined(CONFIG_CPU_S3C2412)
0164     return __raw_readl(S3C2412_GSTATUS1);
0165 #else
0166     return 1UL; /* don't look like an 2400 */
0167 #endif
0168 }
0169 
0170 static unsigned long s3c24xx_read_idcode_v4(void)
0171 {
0172     return __raw_readl(S3C2410_GSTATUS1);
0173 }
0174 
0175 static void s3c24xx_default_idle(void)
0176 {
0177     unsigned long tmp = 0;
0178     int i;
0179 
0180     /* idle the system by using the idle mode which will wait for an
0181      * interrupt to happen before restarting the system.
0182      */
0183 
0184     /* Warning: going into idle state upsets jtag scanning */
0185 
0186     __raw_writel(__raw_readl(S3C2410_CLKCON) | S3C2410_CLKCON_IDLE,
0187              S3C2410_CLKCON);
0188 
0189     /* the samsung port seems to do a loop and then unset idle.. */
0190     for (i = 0; i < 50; i++)
0191         tmp += __raw_readl(S3C2410_CLKCON); /* ensure loop not optimised out */
0192 
0193     /* this bit is not cleared on re-start... */
0194 
0195     __raw_writel(__raw_readl(S3C2410_CLKCON) & ~S3C2410_CLKCON_IDLE,
0196              S3C2410_CLKCON);
0197 }
0198 
0199 static struct samsung_pwm_variant s3c24xx_pwm_variant = {
0200     .bits       = 16,
0201     .div_base   = 1,
0202     .has_tint_cstat = false,
0203     .tclk_mask  = (1 << 4),
0204 };
0205 
0206 void __init s3c24xx_init_io(struct map_desc *mach_desc, int size)
0207 {
0208     arm_pm_idle = s3c24xx_default_idle;
0209 
0210     /* initialise the io descriptors we need for initialisation */
0211     iotable_init(mach_desc, size);
0212     iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
0213 
0214     if (cpu_architecture() >= CPU_ARCH_ARMv5) {
0215         samsung_cpu_id = s3c24xx_read_idcode_v5();
0216     } else {
0217         samsung_cpu_id = s3c24xx_read_idcode_v4();
0218     }
0219 
0220     s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
0221 
0222     samsung_pwm_set_platdata(&s3c24xx_pwm_variant);
0223 }
0224 
0225 void __init s3c24xx_set_timer_source(unsigned int event, unsigned int source)
0226 {
0227     s3c24xx_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1;
0228     s3c24xx_pwm_variant.output_mask &= ~(BIT(event) | BIT(source));
0229 }
0230 
0231 void __init s3c24xx_timer_init(void)
0232 {
0233     unsigned int timer_irqs[SAMSUNG_PWM_NUM] = {
0234         IRQ_TIMER0, IRQ_TIMER1, IRQ_TIMER2, IRQ_TIMER3, IRQ_TIMER4,
0235     };
0236 
0237     samsung_pwm_clocksource_init(S3C_VA_TIMER,
0238                     timer_irqs, &s3c24xx_pwm_variant);
0239 }
0240 
0241 /* Serial port registrations */
0242 
0243 #define S3C2410_PA_UART0      (S3C24XX_PA_UART)
0244 #define S3C2410_PA_UART1      (S3C24XX_PA_UART + 0x4000 )
0245 #define S3C2410_PA_UART2      (S3C24XX_PA_UART + 0x8000 )
0246 #define S3C2443_PA_UART3      (S3C24XX_PA_UART + 0xC000 )
0247 
0248 static struct resource s3c2410_uart0_resource[] = {
0249     [0] = DEFINE_RES_MEM(S3C2410_PA_UART0, SZ_16K),
0250     [1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX0, \
0251             IRQ_S3CUART_ERR0 - IRQ_S3CUART_RX0 + 1, \
0252             NULL, IORESOURCE_IRQ)
0253 };
0254 
0255 static struct resource s3c2410_uart1_resource[] = {
0256     [0] = DEFINE_RES_MEM(S3C2410_PA_UART1, SZ_16K),
0257     [1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX1, \
0258             IRQ_S3CUART_ERR1 - IRQ_S3CUART_RX1 + 1, \
0259             NULL, IORESOURCE_IRQ)
0260 };
0261 
0262 static struct resource s3c2410_uart2_resource[] = {
0263     [0] = DEFINE_RES_MEM(S3C2410_PA_UART2, SZ_16K),
0264     [1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX2, \
0265             IRQ_S3CUART_ERR2 - IRQ_S3CUART_RX2 + 1, \
0266             NULL, IORESOURCE_IRQ)
0267 };
0268 
0269 static struct resource s3c2410_uart3_resource[] = {
0270     [0] = DEFINE_RES_MEM(S3C2443_PA_UART3, SZ_16K),
0271     [1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX3, \
0272             IRQ_S3CUART_ERR3 - IRQ_S3CUART_RX3 + 1, \
0273             NULL, IORESOURCE_IRQ)
0274 };
0275 
0276 struct s3c24xx_uart_resources s3c2410_uart_resources[] __initdata = {
0277     [0] = {
0278         .resources  = s3c2410_uart0_resource,
0279         .nr_resources   = ARRAY_SIZE(s3c2410_uart0_resource),
0280     },
0281     [1] = {
0282         .resources  = s3c2410_uart1_resource,
0283         .nr_resources   = ARRAY_SIZE(s3c2410_uart1_resource),
0284     },
0285     [2] = {
0286         .resources  = s3c2410_uart2_resource,
0287         .nr_resources   = ARRAY_SIZE(s3c2410_uart2_resource),
0288     },
0289     [3] = {
0290         .resources  = s3c2410_uart3_resource,
0291         .nr_resources   = ARRAY_SIZE(s3c2410_uart3_resource),
0292     },
0293 };
0294 
0295 #define s3c24xx_device_dma_mask (*((u64[]) { DMA_BIT_MASK(32) }))
0296 
0297 #if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \
0298     defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442)
0299 static struct resource s3c2410_dma_resource[] = {
0300     [0] = DEFINE_RES_MEM(S3C24XX_PA_DMA, S3C24XX_SZ_DMA),
0301     [1] = DEFINE_RES_IRQ(IRQ_DMA0),
0302     [2] = DEFINE_RES_IRQ(IRQ_DMA1),
0303     [3] = DEFINE_RES_IRQ(IRQ_DMA2),
0304     [4] = DEFINE_RES_IRQ(IRQ_DMA3),
0305 };
0306 #endif
0307 
0308 #if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2442)
0309 static struct s3c24xx_dma_channel s3c2410_dma_channels[DMACH_MAX] = {
0310     [DMACH_XD0] = { S3C24XX_DMA_AHB, true, S3C24XX_DMA_CHANREQ(0, 0), },
0311     [DMACH_XD1] = { S3C24XX_DMA_AHB, true, S3C24XX_DMA_CHANREQ(0, 1), },
0312     [DMACH_SDI] = { S3C24XX_DMA_APB, false, S3C24XX_DMA_CHANREQ(2, 0) |
0313                         S3C24XX_DMA_CHANREQ(2, 2) |
0314                         S3C24XX_DMA_CHANREQ(1, 3),
0315     },
0316     [DMACH_SPI0] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(3, 1), },
0317     [DMACH_SPI1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(2, 3), },
0318     [DMACH_UART0] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(1, 0), },
0319     [DMACH_UART1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(1, 1), },
0320     [DMACH_UART2] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(0, 3), },
0321     [DMACH_TIMER] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(3, 0) |
0322                          S3C24XX_DMA_CHANREQ(3, 2) |
0323                          S3C24XX_DMA_CHANREQ(3, 3),
0324     },
0325     [DMACH_I2S_IN] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(2, 1) |
0326                           S3C24XX_DMA_CHANREQ(1, 2),
0327     },
0328     [DMACH_I2S_OUT] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(0, 2), },
0329     [DMACH_USB_EP1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 0), },
0330     [DMACH_USB_EP2] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 1), },
0331     [DMACH_USB_EP3] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 2), },
0332     [DMACH_USB_EP4] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 3), },
0333 };
0334 
0335 static const struct dma_slave_map s3c2410_dma_slave_map[] = {
0336     { "s3c2410-sdi", "rx-tx", (void *)DMACH_SDI },
0337     { "s3c2410-spi.0", "rx", (void *)DMACH_SPI0_RX },
0338     { "s3c2410-spi.0", "tx", (void *)DMACH_SPI0_TX },
0339     { "s3c2410-spi.1", "rx", (void *)DMACH_SPI1_RX },
0340     { "s3c2410-spi.1", "tx", (void *)DMACH_SPI1_TX },
0341     /*
0342      * The DMA request source[1] (DMACH_UARTx_SRC2) are
0343      * not used in the UART driver.
0344      */
0345     { "s3c2410-uart.0", "rx", (void *)DMACH_UART0 },
0346     { "s3c2410-uart.0", "tx", (void *)DMACH_UART0 },
0347     { "s3c2410-uart.1", "rx", (void *)DMACH_UART1 },
0348     { "s3c2410-uart.1", "tx", (void *)DMACH_UART1 },
0349     { "s3c2410-uart.2", "rx", (void *)DMACH_UART2 },
0350     { "s3c2410-uart.2", "tx", (void *)DMACH_UART2 },
0351     { "s3c24xx-iis", "rx", (void *)DMACH_I2S_IN },
0352     { "s3c24xx-iis", "tx", (void *)DMACH_I2S_OUT },
0353     { "s3c-hsudc", "rx0", (void *)DMACH_USB_EP1 },
0354     { "s3c-hsudc", "tx0", (void *)DMACH_USB_EP1 },
0355     { "s3c-hsudc", "rx1", (void *)DMACH_USB_EP2 },
0356     { "s3c-hsudc", "tx1", (void *)DMACH_USB_EP2 },
0357     { "s3c-hsudc", "rx2", (void *)DMACH_USB_EP3 },
0358     { "s3c-hsudc", "tx2", (void *)DMACH_USB_EP3 },
0359     { "s3c-hsudc", "rx3", (void *)DMACH_USB_EP4 },
0360     { "s3c-hsudc", "tx3", (void *)DMACH_USB_EP4 }
0361 };
0362 
0363 static struct s3c24xx_dma_platdata s3c2410_dma_platdata = {
0364     .num_phy_channels = 4,
0365     .channels = s3c2410_dma_channels,
0366     .num_channels = DMACH_MAX,
0367     .slave_map = s3c2410_dma_slave_map,
0368     .slavecnt = ARRAY_SIZE(s3c2410_dma_slave_map),
0369 };
0370 
0371 struct platform_device s3c2410_device_dma = {
0372     .name       = "s3c2410-dma",
0373     .id     = 0,
0374     .num_resources  = ARRAY_SIZE(s3c2410_dma_resource),
0375     .resource   = s3c2410_dma_resource,
0376     .dev    = {
0377         .dma_mask = &s3c24xx_device_dma_mask,
0378         .coherent_dma_mask = DMA_BIT_MASK(32),
0379         .platform_data = &s3c2410_dma_platdata,
0380     },
0381 };
0382 #endif
0383 
0384 #ifdef CONFIG_CPU_S3C2412
0385 static struct s3c24xx_dma_channel s3c2412_dma_channels[DMACH_MAX] = {
0386     [DMACH_XD0] = { S3C24XX_DMA_AHB, true, 17 },
0387     [DMACH_XD1] = { S3C24XX_DMA_AHB, true, 18 },
0388     [DMACH_SDI] = { S3C24XX_DMA_APB, false, 10 },
0389     [DMACH_SPI0_RX] = { S3C24XX_DMA_APB, true, 1 },
0390     [DMACH_SPI0_TX] = { S3C24XX_DMA_APB, true, 0 },
0391     [DMACH_SPI1_RX] = { S3C24XX_DMA_APB, true, 3 },
0392     [DMACH_SPI1_TX] = { S3C24XX_DMA_APB, true, 2 },
0393     [DMACH_UART0] = { S3C24XX_DMA_APB, true, 19 },
0394     [DMACH_UART1] = { S3C24XX_DMA_APB, true, 21 },
0395     [DMACH_UART2] = { S3C24XX_DMA_APB, true, 23 },
0396     [DMACH_UART0_SRC2] = { S3C24XX_DMA_APB, true, 20 },
0397     [DMACH_UART1_SRC2] = { S3C24XX_DMA_APB, true, 22 },
0398     [DMACH_UART2_SRC2] = { S3C24XX_DMA_APB, true, 24 },
0399     [DMACH_TIMER] = { S3C24XX_DMA_APB, true, 9 },
0400     [DMACH_I2S_IN] = { S3C24XX_DMA_APB, true, 5 },
0401     [DMACH_I2S_OUT] = { S3C24XX_DMA_APB, true, 4 },
0402     [DMACH_USB_EP1] = { S3C24XX_DMA_APB, true, 13 },
0403     [DMACH_USB_EP2] = { S3C24XX_DMA_APB, true, 14 },
0404     [DMACH_USB_EP3] = { S3C24XX_DMA_APB, true, 15 },
0405     [DMACH_USB_EP4] = { S3C24XX_DMA_APB, true, 16 },
0406 };
0407 
0408 static const struct dma_slave_map s3c2412_dma_slave_map[] = {
0409     { "s3c2412-sdi", "rx-tx", (void *)DMACH_SDI },
0410     { "s3c2412-spi.0", "rx", (void *)DMACH_SPI0_RX },
0411     { "s3c2412-spi.0", "tx", (void *)DMACH_SPI0_TX },
0412     { "s3c2412-spi.1", "rx", (void *)DMACH_SPI1_RX },
0413     { "s3c2412-spi.1", "tx", (void *)DMACH_SPI1_TX },
0414     { "s3c2440-uart.0", "rx", (void *)DMACH_UART0 },
0415     { "s3c2440-uart.0", "tx", (void *)DMACH_UART0 },
0416     { "s3c2440-uart.1", "rx", (void *)DMACH_UART1 },
0417     { "s3c2440-uart.1", "tx", (void *)DMACH_UART1 },
0418     { "s3c2440-uart.2", "rx", (void *)DMACH_UART2 },
0419     { "s3c2440-uart.2", "tx", (void *)DMACH_UART2 },
0420     { "s3c2412-iis", "rx", (void *)DMACH_I2S_IN },
0421     { "s3c2412-iis", "tx", (void *)DMACH_I2S_OUT },
0422     { "s3c-hsudc", "rx0", (void *)DMACH_USB_EP1 },
0423     { "s3c-hsudc", "tx0", (void *)DMACH_USB_EP1 },
0424     { "s3c-hsudc", "rx1", (void *)DMACH_USB_EP2 },
0425     { "s3c-hsudc", "tx1", (void *)DMACH_USB_EP2 },
0426     { "s3c-hsudc", "rx2", (void *)DMACH_USB_EP3 },
0427     { "s3c-hsudc", "tx2", (void *)DMACH_USB_EP3 },
0428     { "s3c-hsudc", "rx3", (void *)DMACH_USB_EP4 },
0429     { "s3c-hsudc", "tx3", (void *)DMACH_USB_EP4 }
0430 };
0431 
0432 static struct s3c24xx_dma_platdata s3c2412_dma_platdata = {
0433     .num_phy_channels = 4,
0434     .channels = s3c2412_dma_channels,
0435     .num_channels = DMACH_MAX,
0436     .slave_map = s3c2412_dma_slave_map,
0437     .slavecnt = ARRAY_SIZE(s3c2412_dma_slave_map),
0438 };
0439 
0440 struct platform_device s3c2412_device_dma = {
0441     .name       = "s3c2412-dma",
0442     .id     = 0,
0443     .num_resources  = ARRAY_SIZE(s3c2410_dma_resource),
0444     .resource   = s3c2410_dma_resource,
0445     .dev    = {
0446         .dma_mask = &s3c24xx_device_dma_mask,
0447         .coherent_dma_mask = DMA_BIT_MASK(32),
0448         .platform_data = &s3c2412_dma_platdata,
0449     },
0450 };
0451 #endif
0452 
0453 #if defined(CONFIG_CPU_S3C2440)
0454 static struct s3c24xx_dma_channel s3c2440_dma_channels[DMACH_MAX] = {
0455     [DMACH_XD0] = { S3C24XX_DMA_AHB, true, S3C24XX_DMA_CHANREQ(0, 0), },
0456     [DMACH_XD1] = { S3C24XX_DMA_AHB, true, S3C24XX_DMA_CHANREQ(0, 1), },
0457     [DMACH_SDI] = { S3C24XX_DMA_APB, false, S3C24XX_DMA_CHANREQ(2, 0) |
0458                         S3C24XX_DMA_CHANREQ(6, 1) |
0459                         S3C24XX_DMA_CHANREQ(2, 2) |
0460                         S3C24XX_DMA_CHANREQ(1, 3),
0461     },
0462     [DMACH_SPI0] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(3, 1), },
0463     [DMACH_SPI1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(2, 3), },
0464     [DMACH_UART0] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(1, 0), },
0465     [DMACH_UART1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(1, 1), },
0466     [DMACH_UART2] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(0, 3), },
0467     [DMACH_TIMER] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(3, 0) |
0468                          S3C24XX_DMA_CHANREQ(3, 2) |
0469                          S3C24XX_DMA_CHANREQ(3, 3),
0470     },
0471     [DMACH_I2S_IN] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(2, 1) |
0472                           S3C24XX_DMA_CHANREQ(1, 2),
0473     },
0474     [DMACH_I2S_OUT] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(5, 0) |
0475                            S3C24XX_DMA_CHANREQ(0, 2),
0476     },
0477     [DMACH_PCM_IN] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(6, 0) |
0478                           S3C24XX_DMA_CHANREQ(5, 2),
0479     },
0480     [DMACH_PCM_OUT] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(5, 1) |
0481                           S3C24XX_DMA_CHANREQ(6, 3),
0482     },
0483     [DMACH_MIC_IN] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(6, 2) |
0484                           S3C24XX_DMA_CHANREQ(5, 3),
0485     },
0486     [DMACH_USB_EP1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 0), },
0487     [DMACH_USB_EP2] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 1), },
0488     [DMACH_USB_EP3] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 2), },
0489     [DMACH_USB_EP4] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 3), },
0490 };
0491 
0492 static const struct dma_slave_map s3c2440_dma_slave_map[] = {
0493     /* TODO: DMACH_XD0 */
0494     /* TODO: DMACH_XD1 */
0495     { "s3c2440-sdi", "rx-tx", (void *)DMACH_SDI },
0496     { "s3c2410-spi.0", "rx", (void *)DMACH_SPI0 },
0497     { "s3c2410-spi.0", "tx", (void *)DMACH_SPI0 },
0498     { "s3c2410-spi.1", "rx", (void *)DMACH_SPI1 },
0499     { "s3c2410-spi.1", "tx", (void *)DMACH_SPI1 },
0500     { "s3c2440-uart.0", "rx", (void *)DMACH_UART0 },
0501     { "s3c2440-uart.0", "tx", (void *)DMACH_UART0 },
0502     { "s3c2440-uart.1", "rx", (void *)DMACH_UART1 },
0503     { "s3c2440-uart.1", "tx", (void *)DMACH_UART1 },
0504     { "s3c2440-uart.2", "rx", (void *)DMACH_UART2 },
0505     { "s3c2440-uart.2", "tx", (void *)DMACH_UART2 },
0506     { "s3c2440-uart.3", "rx", (void *)DMACH_UART3 },
0507     { "s3c2440-uart.3", "tx", (void *)DMACH_UART3 },
0508     /* TODO: DMACH_TIMER */
0509     { "s3c24xx-iis", "rx", (void *)DMACH_I2S_IN },
0510     { "s3c24xx-iis", "tx", (void *)DMACH_I2S_OUT },
0511     { "samsung-ac97", "rx", (void *)DMACH_PCM_IN },
0512     { "samsung-ac97", "tx", (void *)DMACH_PCM_OUT },
0513     { "samsung-ac97", "rx", (void *)DMACH_MIC_IN },
0514     { "s3c-hsudc", "rx0", (void *)DMACH_USB_EP1 },
0515     { "s3c-hsudc", "rx1", (void *)DMACH_USB_EP2 },
0516     { "s3c-hsudc", "rx2", (void *)DMACH_USB_EP3 },
0517     { "s3c-hsudc", "rx3", (void *)DMACH_USB_EP4 },
0518     { "s3c-hsudc", "tx0", (void *)DMACH_USB_EP1 },
0519     { "s3c-hsudc", "tx1", (void *)DMACH_USB_EP2 },
0520     { "s3c-hsudc", "tx2", (void *)DMACH_USB_EP3 },
0521     { "s3c-hsudc", "tx3", (void *)DMACH_USB_EP4 }
0522 };
0523 
0524 static struct s3c24xx_dma_platdata s3c2440_dma_platdata = {
0525     .num_phy_channels = 4,
0526     .channels = s3c2440_dma_channels,
0527     .num_channels = DMACH_MAX,
0528     .slave_map = s3c2440_dma_slave_map,
0529     .slavecnt = ARRAY_SIZE(s3c2440_dma_slave_map),
0530 };
0531 
0532 struct platform_device s3c2440_device_dma = {
0533     .name       = "s3c2410-dma",
0534     .id     = 0,
0535     .num_resources  = ARRAY_SIZE(s3c2410_dma_resource),
0536     .resource   = s3c2410_dma_resource,
0537     .dev    = {
0538         .dma_mask = &s3c24xx_device_dma_mask,
0539         .coherent_dma_mask = DMA_BIT_MASK(32),
0540         .platform_data = &s3c2440_dma_platdata,
0541     },
0542 };
0543 #endif
0544 
0545 #if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2416)
0546 static struct resource s3c2443_dma_resource[] = {
0547     [0] = DEFINE_RES_MEM(S3C24XX_PA_DMA, S3C24XX_SZ_DMA),
0548     [1] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA0),
0549     [2] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA1),
0550     [3] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA2),
0551     [4] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA3),
0552     [5] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA4),
0553     [6] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA5),
0554 };
0555 
0556 static struct s3c24xx_dma_channel s3c2443_dma_channels[DMACH_MAX] = {
0557     [DMACH_XD0] = { S3C24XX_DMA_AHB, true, 17 },
0558     [DMACH_XD1] = { S3C24XX_DMA_AHB, true, 18 },
0559     [DMACH_SDI] = { S3C24XX_DMA_APB, false, 10 },
0560     [DMACH_SPI0_RX] = { S3C24XX_DMA_APB, true, 1 },
0561     [DMACH_SPI0_TX] = { S3C24XX_DMA_APB, true, 0 },
0562     [DMACH_SPI1_RX] = { S3C24XX_DMA_APB, true, 3 },
0563     [DMACH_SPI1_TX] = { S3C24XX_DMA_APB, true, 2 },
0564     [DMACH_UART0] = { S3C24XX_DMA_APB, true, 19 },
0565     [DMACH_UART1] = { S3C24XX_DMA_APB, true, 21 },
0566     [DMACH_UART2] = { S3C24XX_DMA_APB, true, 23 },
0567     [DMACH_UART3] = { S3C24XX_DMA_APB, true, 25 },
0568     [DMACH_UART0_SRC2] = { S3C24XX_DMA_APB, true, 20 },
0569     [DMACH_UART1_SRC2] = { S3C24XX_DMA_APB, true, 22 },
0570     [DMACH_UART2_SRC2] = { S3C24XX_DMA_APB, true, 24 },
0571     [DMACH_UART3_SRC2] = { S3C24XX_DMA_APB, true, 26 },
0572     [DMACH_TIMER] = { S3C24XX_DMA_APB, true, 9 },
0573     [DMACH_I2S_IN] = { S3C24XX_DMA_APB, true, 5 },
0574     [DMACH_I2S_OUT] = { S3C24XX_DMA_APB, true, 4 },
0575     [DMACH_PCM_IN] = { S3C24XX_DMA_APB, true, 28 },
0576     [DMACH_PCM_OUT] = { S3C24XX_DMA_APB, true, 27 },
0577     [DMACH_MIC_IN] = { S3C24XX_DMA_APB, true, 29 },
0578 };
0579 
0580 static const struct dma_slave_map s3c2443_dma_slave_map[] = {
0581     { "s3c2440-sdi", "rx-tx", (void *)DMACH_SDI },
0582     { "s3c2443-spi.0", "rx", (void *)DMACH_SPI0_RX },
0583     { "s3c2443-spi.0", "tx", (void *)DMACH_SPI0_TX },
0584     { "s3c2443-spi.1", "rx", (void *)DMACH_SPI1_RX },
0585     { "s3c2443-spi.1", "tx", (void *)DMACH_SPI1_TX },
0586     { "s3c2440-uart.0", "rx", (void *)DMACH_UART0 },
0587     { "s3c2440-uart.0", "tx", (void *)DMACH_UART0 },
0588     { "s3c2440-uart.1", "rx", (void *)DMACH_UART1 },
0589     { "s3c2440-uart.1", "tx", (void *)DMACH_UART1 },
0590     { "s3c2440-uart.2", "rx", (void *)DMACH_UART2 },
0591     { "s3c2440-uart.2", "tx", (void *)DMACH_UART2 },
0592     { "s3c2440-uart.3", "rx", (void *)DMACH_UART3 },
0593     { "s3c2440-uart.3", "tx", (void *)DMACH_UART3 },
0594     { "s3c24xx-iis", "rx", (void *)DMACH_I2S_IN },
0595     { "s3c24xx-iis", "tx", (void *)DMACH_I2S_OUT },
0596 };
0597 
0598 static struct s3c24xx_dma_platdata s3c2443_dma_platdata = {
0599     .num_phy_channels = 6,
0600     .channels = s3c2443_dma_channels,
0601     .num_channels = DMACH_MAX,
0602     .slave_map = s3c2443_dma_slave_map,
0603     .slavecnt = ARRAY_SIZE(s3c2443_dma_slave_map),
0604 };
0605 
0606 struct platform_device s3c2443_device_dma = {
0607     .name       = "s3c2443-dma",
0608     .id     = 0,
0609     .num_resources  = ARRAY_SIZE(s3c2443_dma_resource),
0610     .resource   = s3c2443_dma_resource,
0611     .dev    = {
0612         .dma_mask = &s3c24xx_device_dma_mask,
0613         .coherent_dma_mask = DMA_BIT_MASK(32),
0614         .platform_data = &s3c2443_dma_platdata,
0615     },
0616 };
0617 #endif
0618 
0619 #if defined(CONFIG_COMMON_CLK) && defined(CONFIG_CPU_S3C2410)
0620 void __init s3c2410_init_clocks(int xtal)
0621 {
0622     s3c2410_common_clk_init(NULL, xtal, 0, S3C24XX_VA_CLKPWR);
0623 }
0624 #endif
0625 
0626 #ifdef CONFIG_CPU_S3C2412
0627 void __init s3c2412_init_clocks(int xtal)
0628 {
0629     s3c2412_common_clk_init(NULL, xtal, 0, S3C24XX_VA_CLKPWR);
0630 }
0631 #endif
0632 
0633 #ifdef CONFIG_CPU_S3C2416
0634 void __init s3c2416_init_clocks(int xtal)
0635 {
0636     s3c2443_common_clk_init(NULL, xtal, 0, S3C24XX_VA_CLKPWR);
0637 }
0638 #endif
0639 
0640 #if defined(CONFIG_COMMON_CLK) && defined(CONFIG_CPU_S3C2440)
0641 void __init s3c2440_init_clocks(int xtal)
0642 {
0643     s3c2410_common_clk_init(NULL, xtal, 1, S3C24XX_VA_CLKPWR);
0644 }
0645 #endif
0646 
0647 #if defined(CONFIG_COMMON_CLK) && defined(CONFIG_CPU_S3C2442)
0648 void __init s3c2442_init_clocks(int xtal)
0649 {
0650     s3c2410_common_clk_init(NULL, xtal, 2, S3C24XX_VA_CLKPWR);
0651 }
0652 #endif
0653 
0654 #ifdef CONFIG_CPU_S3C2443
0655 void __init s3c2443_init_clocks(int xtal)
0656 {
0657     s3c2443_common_clk_init(NULL, xtal, 1, S3C24XX_VA_CLKPWR);
0658 }
0659 #endif
0660 
0661 #if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2440) || \
0662     defined(CONFIG_CPU_S3C2442)
0663 static struct resource s3c2410_dclk_resource[] = {
0664     [0] = DEFINE_RES_MEM(0x56000084, 0x4),
0665 };
0666 
0667 static struct s3c2410_clk_platform_data s3c_clk_platform_data = {
0668     .modify_misccr = s3c2410_modify_misccr,
0669 };
0670 
0671 struct platform_device s3c2410_device_dclk = {
0672     .name       = "s3c2410-dclk",
0673     .id     = 0,
0674     .num_resources  = ARRAY_SIZE(s3c2410_dclk_resource),
0675     .resource   = s3c2410_dclk_resource,
0676     .dev        = {
0677         .platform_data = &s3c_clk_platform_data,
0678     },
0679 };
0680 #endif
0681 
0682 #ifndef CONFIG_COMPILE_TEST
0683 #pragma message "The platform is deprecated and scheduled for removal. " \
0684         "Please reach to the maintainers of the platform " \
0685         "and linux-samsung-soc@vger.kernel.org if you still use it." \
0686         "Without such feedback, the platform will be removed after 2022."
0687 #endif
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