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0007 #ifndef __ARCH_ARM_MACH_S3C24XX_S3C2412_POWER_H
0008 #define __ARCH_ARM_MACH_S3C24XX_S3C2412_POWER_H __FILE__
0009
0010 #define S3C24XX_PWRREG(x) ((x) + S3C24XX_VA_CLKPWR)
0011
0012 #define S3C2412_PWRMODECON S3C24XX_PWRREG(0x20)
0013 #define S3C2412_PWRCFG S3C24XX_PWRREG(0x24)
0014
0015 #define S3C2412_INFORM0 S3C24XX_PWRREG(0x70)
0016 #define S3C2412_INFORM1 S3C24XX_PWRREG(0x74)
0017 #define S3C2412_INFORM2 S3C24XX_PWRREG(0x78)
0018 #define S3C2412_INFORM3 S3C24XX_PWRREG(0x7C)
0019
0020 #define S3C2412_PWRCFG_BATF_IRQ (1 << 0)
0021 #define S3C2412_PWRCFG_BATF_IGNORE (2 << 0)
0022 #define S3C2412_PWRCFG_BATF_SLEEP (3 << 0)
0023 #define S3C2412_PWRCFG_BATF_MASK (3 << 0)
0024
0025 #define S3C2412_PWRCFG_STANDBYWFI_IGNORE (0 << 6)
0026 #define S3C2412_PWRCFG_STANDBYWFI_IDLE (1 << 6)
0027 #define S3C2412_PWRCFG_STANDBYWFI_STOP (2 << 6)
0028 #define S3C2412_PWRCFG_STANDBYWFI_SLEEP (3 << 6)
0029 #define S3C2412_PWRCFG_STANDBYWFI_MASK (3 << 6)
0030
0031 #define S3C2412_PWRCFG_RTC_MASKIRQ (1 << 8)
0032 #define S3C2412_PWRCFG_NAND_NORST (1 << 9)
0033
0034 #endif