arm/mach-s3c/regs-usb-hsotg-phy-s3c64xx.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright 2008 Openmoko, Inc.
0004  * Copyright 2008 Simtec Electronics
0005  *      http://armlinux.simtec.co.uk/
0006  *      Ben Dooks <ben@simtec.co.uk>
0007  *
0008  * S3C - USB2.0 Highspeed/OtG device PHY registers
0009 */
0010
0011 /* Note, this is a separate header file as some of the clock framework
0012  * needs to touch this if the clk_48m is used as the USB OHCI or other
0013  * peripheral source.
0014 */
0015
0016 #ifndef __PLAT_S3C64XX_REGS_USB_HSOTG_PHY_H
0017 #define __PLAT_S3C64XX_REGS_USB_HSOTG_PHY_H __FILE__
0018
0019 /* S3C64XX_PA_USB_HSPHY */
0020
0021 #define S3C_HSOTG_PHYREG(x) ((x) + S3C_VA_USB_HSPHY)
0022
0023 #define S3C_PHYPWR              S3C_HSOTG_PHYREG(0x00)
0024 #define S3C_PHYPWR_NORMAL_MASK          (0x19 << 0)
0025 #define S3C_PHYPWR_OTG_DISABLE          (1 << 4)
0026 #define S3C_PHYPWR_ANALOG_POWERDOWN     (1 << 3)
0027 #define SRC_PHYPWR_FORCE_SUSPEND        (1 << 1)
0028
0029 #define S3C_PHYCLK              S3C_HSOTG_PHYREG(0x04)
0030 #define S3C_PHYCLK_MODE_USB11           (1 << 6)
0031 #define S3C_PHYCLK_EXT_OSC          (1 << 5)
0032 #define S3C_PHYCLK_CLK_FORCE            (1 << 4)
0033 #define S3C_PHYCLK_ID_PULL          (1 << 2)
0034 #define S3C_PHYCLK_CLKSEL_MASK          (0x3 << 0)
0035 #define S3C_PHYCLK_CLKSEL_SHIFT         (0)
0036 #define S3C_PHYCLK_CLKSEL_48M           (0x0 << 0)
0037 #define S3C_PHYCLK_CLKSEL_12M           (0x2 << 0)
0038 #define S3C_PHYCLK_CLKSEL_24M           (0x3 << 0)
0039
0040 #define S3C_RSTCON              S3C_HSOTG_PHYREG(0x08)
0041 #define S3C_RSTCON_PHYCLK           (1 << 2)
0042 #define S3C_RSTCON_HCLK             (1 << 1)
0043 #define S3C_RSTCON_PHY              (1 << 0)
0044
0045 #define S3C_PHYTUNE             S3C_HSOTG_PHYREG(0x20)
0046
0047 #endif /* __PLAT_S3C64XX_REGS_USB_HSOTG_PHY_H */