arm/mach-s3c/regs-syscon-power-s3c64xx.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright 2008 Openmoko, Inc.
0004  * Copyright 2008 Simtec Electronics
0005  *      http://armlinux.simtec.co.uk/
0006  *      Ben Dooks <ben@simtec.co.uk>
0007  *
0008  * S3C64XX - syscon power and sleep control registers
0009 */
0010
0011 #ifndef __MACH_S3C64XX_REGS_SYSCON_POWER_H
0012 #define __MACH_S3C64XX_REGS_SYSCON_POWER_H __FILE__
0013
0014 #define S3C64XX_PWR_CFG             S3C_SYSREG(0x804)
0015
0016 #define S3C64XX_PWRCFG_OSC_OTG_DISABLE      (1 << 17)
0017 #define S3C64XX_PWRCFG_MMC2_DISABLE     (1 << 16)
0018 #define S3C64XX_PWRCFG_MMC1_DISABLE     (1 << 15)
0019 #define S3C64XX_PWRCFG_MMC0_DISABLE     (1 << 14)
0020 #define S3C64XX_PWRCFG_HSI_DISABLE      (1 << 13)
0021 #define S3C64XX_PWRCFG_TS_DISABLE       (1 << 12)
0022 #define S3C64XX_PWRCFG_RTC_TICK_DISABLE     (1 << 11)
0023 #define S3C64XX_PWRCFG_RTC_ALARM_DISABLE    (1 << 10)
0024 #define S3C64XX_PWRCFG_MSM_DISABLE      (1 << 9)
0025 #define S3C64XX_PWRCFG_KEY_DISABLE      (1 << 8)
0026 #define S3C64XX_PWRCFG_BATF_DISABLE     (1 << 7)
0027
0028 #define S3C64XX_PWRCFG_CFG_WFI_MASK     (0x3 << 5)
0029 #define S3C64XX_PWRCFG_CFG_WFI_SHIFT        (5)
0030 #define S3C64XX_PWRCFG_CFG_WFI_IGNORE       (0x0 << 5)
0031 #define S3C64XX_PWRCFG_CFG_WFI_IDLE     (0x1 << 5)
0032 #define S3C64XX_PWRCFG_CFG_WFI_STOP     (0x2 << 5)
0033 #define S3C64XX_PWRCFG_CFG_WFI_SLEEP        (0x3 << 5)
0034
0035 #define S3C64XX_PWRCFG_CFG_BATFLT_MASK      (0x3 << 3)
0036 #define S3C64XX_PWRCFG_CFG_BATFLT_SHIFT     (3)
0037 #define S3C64XX_PWRCFG_CFG_BATFLT_IGNORE    (0x0 << 3)
0038 #define S3C64XX_PWRCFG_CFG_BATFLT_IRQ       (0x1 << 3)
0039 #define S3C64XX_PWRCFG_CFG_BATFLT_SLEEP     (0x3 << 3)
0040
0041 #define S3C64XX_PWRCFG_CFG_BAT_WAKE     (1 << 2)
0042 #define S3C64XX_PWRCFG_OSC27_EN         (1 << 0)
0043
0044 #define S3C64XX_EINT_MASK           S3C_SYSREG(0x808)
0045
0046 #define S3C64XX_NORMAL_CFG          S3C_SYSREG(0x810)
0047
0048 #define S3C64XX_NORMALCFG_IROM_ON       (1 << 30)
0049 #define S3C64XX_NORMALCFG_DOMAIN_ETM_ON     (1 << 16)
0050 #define S3C64XX_NORMALCFG_DOMAIN_S_ON       (1 << 15)
0051 #define S3C64XX_NORMALCFG_DOMAIN_F_ON       (1 << 14)
0052 #define S3C64XX_NORMALCFG_DOMAIN_P_ON       (1 << 13)
0053 #define S3C64XX_NORMALCFG_DOMAIN_I_ON       (1 << 12)
0054 #define S3C64XX_NORMALCFG_DOMAIN_G_ON       (1 << 10)
0055 #define S3C64XX_NORMALCFG_DOMAIN_V_ON       (1 << 9)
0056
0057 #define S3C64XX_STOP_CFG            S3C_SYSREG(0x814)
0058
0059 #define S3C64XX_STOPCFG_MEMORY_ARM_ON       (1 << 29)
0060 #define S3C64XX_STOPCFG_TOP_MEMORY_ON       (1 << 20)
0061 #define S3C64XX_STOPCFG_ARM_LOGIC_ON        (1 << 17)
0062 #define S3C64XX_STOPCFG_TOP_LOGIC_ON        (1 << 8)
0063 #define S3C64XX_STOPCFG_OSC_EN          (1 << 0)
0064
0065 #define S3C64XX_SLEEP_CFG           S3C_SYSREG(0x818)
0066
0067 #define S3C64XX_SLEEPCFG_OSC_EN         (1 << 0)
0068
0069 #define S3C64XX_STOP_MEM_CFG            S3C_SYSREG(0x81c)
0070
0071 #define S3C64XX_STOPMEMCFG_MODEMIF_RETAIN   (1 << 6)
0072 #define S3C64XX_STOPMEMCFG_HOSTIF_RETAIN    (1 << 5)
0073 #define S3C64XX_STOPMEMCFG_OTG_RETAIN       (1 << 4)
0074 #define S3C64XX_STOPMEMCFG_HSMCC_RETAIN     (1 << 3)
0075 #define S3C64XX_STOPMEMCFG_IROM_RETAIN      (1 << 2)
0076 #define S3C64XX_STOPMEMCFG_IRDA_RETAIN      (1 << 1)
0077 #define S3C64XX_STOPMEMCFG_NFCON_RETAIN     (1 << 0)
0078
0079 #define S3C64XX_OSC_STABLE          S3C_SYSREG(0x824)
0080 #define S3C64XX_PWR_STABLE          S3C_SYSREG(0x828)
0081
0082 #define S3C64XX_WAKEUP_STAT         S3C_SYSREG(0x908)
0083
0084 #define S3C64XX_WAKEUPSTAT_MMC2         (1 << 11)
0085 #define S3C64XX_WAKEUPSTAT_MMC1         (1 << 10)
0086 #define S3C64XX_WAKEUPSTAT_MMC0         (1 << 9)
0087 #define S3C64XX_WAKEUPSTAT_HSI          (1 << 8)
0088 #define S3C64XX_WAKEUPSTAT_BATFLT       (1 << 6)
0089 #define S3C64XX_WAKEUPSTAT_MSM          (1 << 5)
0090 #define S3C64XX_WAKEUPSTAT_KEY          (1 << 4)
0091 #define S3C64XX_WAKEUPSTAT_TS           (1 << 3)
0092 #define S3C64XX_WAKEUPSTAT_RTC_TICK     (1 << 2)
0093 #define S3C64XX_WAKEUPSTAT_RTC_ALARM        (1 << 1)
0094 #define S3C64XX_WAKEUPSTAT_EINT         (1 << 0)
0095
0096 #define S3C64XX_BLK_PWR_STAT            S3C_SYSREG(0x90c)
0097
0098 #define S3C64XX_BLKPWRSTAT_G            (1 << 7)
0099 #define S3C64XX_BLKPWRSTAT_ETM          (1 << 6)
0100 #define S3C64XX_BLKPWRSTAT_S            (1 << 5)
0101 #define S3C64XX_BLKPWRSTAT_F            (1 << 4)
0102 #define S3C64XX_BLKPWRSTAT_P            (1 << 3)
0103 #define S3C64XX_BLKPWRSTAT_I            (1 << 2)
0104 #define S3C64XX_BLKPWRSTAT_V            (1 << 1)
0105 #define S3C64XX_BLKPWRSTAT_TOP          (1 << 0)
0106
0107 #define S3C64XX_INFORM0             S3C_SYSREG(0xA00)
0108 #define S3C64XX_INFORM1             S3C_SYSREG(0xA04)
0109 #define S3C64XX_INFORM2             S3C_SYSREG(0xA08)
0110 #define S3C64XX_INFORM3             S3C_SYSREG(0xA0C)
0111
0112 #endif /* __MACH_S3C64XX_REGS_SYSCON_POWER_H */