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0008 #ifndef __MACH_S3C64XX_REGS_SROM_H
0009 #define __MACH_S3C64XX_REGS_SROM_H __FILE__
0010
0011 #define S3C64XX_SROMREG(x) (S3C_VA_MEM + (x))
0012
0013 #define S3C64XX_SROM_BW S3C64XX_SROMREG(0)
0014 #define S3C64XX_SROM_BC0 S3C64XX_SROMREG(4)
0015 #define S3C64XX_SROM_BC1 S3C64XX_SROMREG(8)
0016 #define S3C64XX_SROM_BC2 S3C64XX_SROMREG(0xc)
0017 #define S3C64XX_SROM_BC3 S3C64XX_SROMREG(0x10)
0018 #define S3C64XX_SROM_BC4 S3C64XX_SROMREG(0x14)
0019 #define S3C64XX_SROM_BC5 S3C64XX_SROMREG(0x18)
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0025 #define S3C64XX_SROM_BW__DATAWIDTH__SHIFT 0
0026 #define S3C64XX_SROM_BW__WAITENABLE__SHIFT 2
0027 #define S3C64XX_SROM_BW__BYTEENABLE__SHIFT 3
0028 #define S3C64XX_SROM_BW__CS_MASK 0xf
0029
0030 #define S3C64XX_SROM_BW__NCS0__SHIFT 0
0031 #define S3C64XX_SROM_BW__NCS1__SHIFT 4
0032 #define S3C64XX_SROM_BW__NCS2__SHIFT 8
0033 #define S3C64XX_SROM_BW__NCS3__SHIFT 0xc
0034 #define S3C64XX_SROM_BW__NCS4__SHIFT 0x10
0035
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0038
0039
0040 #define S3C64XX_SROM_BCX__PMC__SHIFT 0
0041 #define S3C64XX_SROM_BCX__PMC__MASK 3
0042 #define S3C64XX_SROM_BCX__TACP__SHIFT 4
0043 #define S3C64XX_SROM_BCX__TACP__MASK 0xf
0044 #define S3C64XX_SROM_BCX__TCAH__SHIFT 8
0045 #define S3C64XX_SROM_BCX__TCAH__MASK 0xf
0046 #define S3C64XX_SROM_BCX__TCOH__SHIFT 12
0047 #define S3C64XX_SROM_BCX__TCOH__MASK 0xf
0048 #define S3C64XX_SROM_BCX__TACC__SHIFT 16
0049 #define S3C64XX_SROM_BCX__TACC__MASK 0x1f
0050 #define S3C64XX_SROM_BCX__TCOS__SHIFT 24
0051 #define S3C64XX_SROM_BCX__TCOS__MASK 0xf
0052 #define S3C64XX_SROM_BCX__TACS__SHIFT 28
0053 #define S3C64XX_SROM_BCX__TACS__MASK 0xf
0054
0055 #endif