arm/mach-s3c/regs-s3c2443-clock.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright (c) 2007 Simtec Electronics
0004  *  Ben Dooks <ben@simtec.co.uk>
0005  *  http://armlinux.simtec.co.uk/
0006  *
0007  * S3C2443 clock register definitions
0008  */
0009
0010 #ifndef __ASM_ARM_REGS_S3C2443_CLOCK
0011 #define __ASM_ARM_REGS_S3C2443_CLOCK
0012
0013 #include <linux/delay.h>
0014 #include "map-s3c.h"
0015
0016 #define S3C2443_CLKREG(x)       ((x) + S3C24XX_VA_CLKPWR)
0017
0018 #define S3C2443_PLLCON_MDIVSHIFT    16
0019 #define S3C2443_PLLCON_PDIVSHIFT    8
0020 #define S3C2443_PLLCON_SDIVSHIFT    0
0021 #define S3C2443_PLLCON_MDIVMASK     ((1<<(1+(23-16)))-1)
0022 #define S3C2443_PLLCON_PDIVMASK     ((1<<(1+(9-8)))-1)
0023 #define S3C2443_PLLCON_SDIVMASK     (3)
0024
0025 #define S3C2443_MPLLCON         S3C2443_CLKREG(0x10)
0026 #define S3C2443_EPLLCON         S3C2443_CLKREG(0x18)
0027 #define S3C2443_CLKSRC          S3C2443_CLKREG(0x20)
0028 #define S3C2443_CLKDIV0         S3C2443_CLKREG(0x24)
0029 #define S3C2443_CLKDIV1         S3C2443_CLKREG(0x28)
0030 #define S3C2443_HCLKCON         S3C2443_CLKREG(0x30)
0031 #define S3C2443_PCLKCON         S3C2443_CLKREG(0x34)
0032 #define S3C2443_SCLKCON         S3C2443_CLKREG(0x38)
0033 #define S3C2443_PWRMODE         S3C2443_CLKREG(0x40)
0034 #define S3C2443_SWRST           S3C2443_CLKREG(0x44)
0035 #define S3C2443_BUSPRI0         S3C2443_CLKREG(0x50)
0036 #define S3C2443_SYSID           S3C2443_CLKREG(0x5C)
0037 #define S3C2443_PWRCFG          S3C2443_CLKREG(0x60)
0038 #define S3C2443_RSTCON          S3C2443_CLKREG(0x64)
0039 #define S3C2443_PHYCTRL         S3C2443_CLKREG(0x80)
0040 #define S3C2443_PHYPWR          S3C2443_CLKREG(0x84)
0041 #define S3C2443_URSTCON         S3C2443_CLKREG(0x88)
0042 #define S3C2443_UCLKCON         S3C2443_CLKREG(0x8C)
0043
0044 #define S3C2443_PLLCON_OFF      (1<<24)
0045
0046 #define S3C2443_CLKSRC_EPLLREF_XTAL (2<<7)
0047 #define S3C2443_CLKSRC_EPLLREF_EXTCLK   (3<<7)
0048 #define S3C2443_CLKSRC_EPLLREF_MPLLREF  (0<<7)
0049 #define S3C2443_CLKSRC_EPLLREF_MPLLREF2 (1<<7)
0050 #define S3C2443_CLKSRC_EPLLREF_MASK (3<<7)
0051
0052 #define S3C2443_CLKSRC_EXTCLK_DIV   (1<<3)
0053
0054 #define S3C2443_CLKDIV0_HALF_HCLK   (1<<3)
0055 #define S3C2443_CLKDIV0_HALF_PCLK   (1<<2)
0056
0057 #define S3C2443_CLKDIV0_HCLKDIV_MASK    (3<<0)
0058
0059 #define S3C2443_CLKDIV0_EXTDIV_MASK (3<<6)
0060 #define S3C2443_CLKDIV0_EXTDIV_SHIFT    (6)
0061
0062 #define S3C2443_CLKDIV0_PREDIV_MASK (3<<4)
0063 #define S3C2443_CLKDIV0_PREDIV_SHIFT    (4)
0064
0065 #define S3C2416_CLKDIV0_ARMDIV_MASK (7 << 9)
0066 #define S3C2443_CLKDIV0_ARMDIV_MASK (15<<9)
0067 #define S3C2443_CLKDIV0_ARMDIV_SHIFT    (9)
0068 #define S3C2443_CLKDIV0_ARMDIV_1    (0<<9)
0069 #define S3C2443_CLKDIV0_ARMDIV_2    (8<<9)
0070 #define S3C2443_CLKDIV0_ARMDIV_3    (2<<9)
0071 #define S3C2443_CLKDIV0_ARMDIV_4    (9<<9)
0072 #define S3C2443_CLKDIV0_ARMDIV_6    (10<<9)
0073 #define S3C2443_CLKDIV0_ARMDIV_8    (11<<9)
0074 #define S3C2443_CLKDIV0_ARMDIV_12   (13<<9)
0075 #define S3C2443_CLKDIV0_ARMDIV_16   (15<<9)
0076
0077 /* S3C2443_CLKDIV1 removed, only used in clock.c code */
0078
0079 #define S3C2443_CLKCON_NAND
0080
0081 #define S3C2443_HCLKCON_DMA0        (1<<0)
0082 #define S3C2443_HCLKCON_DMA1        (1<<1)
0083 #define S3C2443_HCLKCON_DMA2        (1<<2)
0084 #define S3C2443_HCLKCON_DMA3        (1<<3)
0085 #define S3C2443_HCLKCON_DMA4        (1<<4)
0086 #define S3C2443_HCLKCON_DMA5        (1<<5)
0087 #define S3C2443_HCLKCON_CAMIF       (1<<8)
0088 #define S3C2443_HCLKCON_LCDC        (1<<9)
0089 #define S3C2443_HCLKCON_USBH        (1<<11)
0090 #define S3C2443_HCLKCON_USBD        (1<<12)
0091 #define S3C2416_HCLKCON_HSMMC0      (1<<15)
0092 #define S3C2443_HCLKCON_HSMMC       (1<<16)
0093 #define S3C2443_HCLKCON_CFC     (1<<17)
0094 #define S3C2443_HCLKCON_SSMC        (1<<18)
0095 #define S3C2443_HCLKCON_DRAMC       (1<<19)
0096
0097 #define S3C2443_PCLKCON_UART0       (1<<0)
0098 #define S3C2443_PCLKCON_UART1       (1<<1)
0099 #define S3C2443_PCLKCON_UART2       (1<<2)
0100 #define S3C2443_PCLKCON_UART3       (1<<3)
0101 #define S3C2443_PCLKCON_IIC     (1<<4)
0102 #define S3C2443_PCLKCON_SDI     (1<<5)
0103 #define S3C2443_PCLKCON_HSSPI       (1<<6)
0104 #define S3C2443_PCLKCON_ADC     (1<<7)
0105 #define S3C2443_PCLKCON_AC97        (1<<8)
0106 #define S3C2443_PCLKCON_IIS     (1<<9)
0107 #define S3C2443_PCLKCON_PWMT        (1<<10)
0108 #define S3C2443_PCLKCON_WDT     (1<<11)
0109 #define S3C2443_PCLKCON_RTC     (1<<12)
0110 #define S3C2443_PCLKCON_GPIO        (1<<13)
0111 #define S3C2443_PCLKCON_SPI0        (1<<14)
0112 #define S3C2443_PCLKCON_SPI1        (1<<15)
0113
0114 #define S3C2443_SCLKCON_DDRCLK      (1<<16)
0115 #define S3C2443_SCLKCON_SSMCCLK     (1<<15)
0116 #define S3C2443_SCLKCON_HSSPICLK    (1<<14)
0117 #define S3C2443_SCLKCON_HSMMCCLK_EXT    (1<<13)
0118 #define S3C2443_SCLKCON_HSMMCCLK_EPLL   (1<<12)
0119 #define S3C2443_SCLKCON_CAMCLK      (1<<11)
0120 #define S3C2443_SCLKCON_DISPCLK     (1<<10)
0121 #define S3C2443_SCLKCON_I2SCLK      (1<<9)
0122 #define S3C2443_SCLKCON_UARTCLK     (1<<8)
0123 #define S3C2443_SCLKCON_USBHOST     (1<<1)
0124
0125 #define S3C2443_PWRCFG_SLEEP        (1<<15)
0126
0127 #define S3C2443_PWRCFG_USBPHY       (1 << 4)
0128
0129 #define S3C2443_URSTCON_FUNCRST     (1 << 2)
0130 #define S3C2443_URSTCON_PHYRST      (1 << 0)
0131
0132 #define S3C2443_PHYCTRL_CLKSEL      (1 << 3)
0133 #define S3C2443_PHYCTRL_EXTCLK      (1 << 2)
0134 #define S3C2443_PHYCTRL_PLLSEL      (1 << 1)
0135 #define S3C2443_PHYCTRL_DSPORT      (1 << 0)
0136
0137 #define S3C2443_PHYPWR_COMMON_ON    (1 << 31)
0138 #define S3C2443_PHYPWR_ANALOG_PD    (1 << 4)
0139 #define S3C2443_PHYPWR_PLL_REFCLK   (1 << 3)
0140 #define S3C2443_PHYPWR_XO_ON        (1 << 2)
0141 #define S3C2443_PHYPWR_PLL_PWRDN    (1 << 1)
0142 #define S3C2443_PHYPWR_FSUSPEND     (1 << 0)
0143
0144 #define S3C2443_UCLKCON_DETECT_VBUS (1 << 31)
0145 #define S3C2443_UCLKCON_FUNC_CLKEN  (1 << 2)
0146 #define S3C2443_UCLKCON_TCLKEN      (1 << 0)
0147
0148 #include <asm/div64.h>
0149
0150 static inline unsigned int
0151 s3c2443_get_mpll(unsigned int pllval, unsigned int baseclk)
0152 {
0153     unsigned int mdiv, pdiv, sdiv;
0154     uint64_t fvco;
0155
0156     mdiv = pllval >> S3C2443_PLLCON_MDIVSHIFT;
0157     pdiv = pllval >> S3C2443_PLLCON_PDIVSHIFT;
0158     sdiv = pllval >> S3C2443_PLLCON_SDIVSHIFT;
0159
0160     mdiv &= S3C2443_PLLCON_MDIVMASK;
0161     pdiv &= S3C2443_PLLCON_PDIVMASK;
0162     sdiv &= S3C2443_PLLCON_SDIVMASK;
0163
0164     fvco = (uint64_t)baseclk * (2 * (mdiv + 8));
0165     do_div(fvco, pdiv << sdiv);
0166
0167     return (unsigned int)fvco;
0168 }
0169
0170 static inline unsigned int
0171 s3c2443_get_epll(unsigned int pllval, unsigned int baseclk)
0172 {
0173     unsigned int mdiv, pdiv, sdiv;
0174     uint64_t fvco;
0175
0176     mdiv = pllval >> S3C2443_PLLCON_MDIVSHIFT;
0177     pdiv = pllval >> S3C2443_PLLCON_PDIVSHIFT;
0178     sdiv = pllval >> S3C2443_PLLCON_SDIVSHIFT;
0179
0180     mdiv &= S3C2443_PLLCON_MDIVMASK;
0181     pdiv &= S3C2443_PLLCON_PDIVMASK;
0182     sdiv &= S3C2443_PLLCON_SDIVMASK;
0183
0184     fvco = (uint64_t)baseclk * (mdiv + 8);
0185     do_div(fvco, (pdiv + 2) << sdiv);
0186
0187     return (unsigned int)fvco;
0188 }
0189
0190 static inline void s3c_hsudc_init_phy(void)
0191 {
0192     u32 cfg;
0193
0194     cfg = readl(S3C2443_PWRCFG) | S3C2443_PWRCFG_USBPHY;
0195     writel(cfg, S3C2443_PWRCFG);
0196
0197     cfg = readl(S3C2443_URSTCON);
0198     cfg |= (S3C2443_URSTCON_FUNCRST | S3C2443_URSTCON_PHYRST);
0199     writel(cfg, S3C2443_URSTCON);
0200     mdelay(1);
0201
0202     cfg = readl(S3C2443_URSTCON);
0203     cfg &= ~(S3C2443_URSTCON_FUNCRST | S3C2443_URSTCON_PHYRST);
0204     writel(cfg, S3C2443_URSTCON);
0205
0206     cfg = readl(S3C2443_PHYCTRL);
0207     cfg &= ~(S3C2443_PHYCTRL_CLKSEL | S3C2443_PHYCTRL_DSPORT);
0208     cfg |= (S3C2443_PHYCTRL_EXTCLK | S3C2443_PHYCTRL_PLLSEL);
0209     writel(cfg, S3C2443_PHYCTRL);
0210
0211     cfg = readl(S3C2443_PHYPWR);
0212     cfg &= ~(S3C2443_PHYPWR_FSUSPEND | S3C2443_PHYPWR_PLL_PWRDN |
0213         S3C2443_PHYPWR_XO_ON | S3C2443_PHYPWR_PLL_REFCLK |
0214         S3C2443_PHYPWR_ANALOG_PD);
0215     cfg |= S3C2443_PHYPWR_COMMON_ON;
0216     writel(cfg, S3C2443_PHYPWR);
0217
0218     cfg = readl(S3C2443_UCLKCON);
0219     cfg |= (S3C2443_UCLKCON_DETECT_VBUS | S3C2443_UCLKCON_FUNC_CLKEN |
0220         S3C2443_UCLKCON_TCLKEN);
0221     writel(cfg, S3C2443_UCLKCON);
0222 }
0223
0224 static inline void s3c_hsudc_uninit_phy(void)
0225 {
0226     u32 cfg;
0227
0228     cfg = readl(S3C2443_PWRCFG) & ~S3C2443_PWRCFG_USBPHY;
0229     writel(cfg, S3C2443_PWRCFG);
0230
0231     writel(S3C2443_PHYPWR_FSUSPEND, S3C2443_PHYPWR);
0232
0233     cfg = readl(S3C2443_UCLKCON) & ~S3C2443_UCLKCON_FUNC_CLKEN;
0234     writel(cfg, S3C2443_UCLKCON);
0235 }
0236
0237 #endif /*  __ASM_ARM_REGS_S3C2443_CLOCK */
0238