arm/mach-s3c/regs-mem-s3c24xx.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
0004  *      http://www.simtec.co.uk/products/SWLINUX/
0005  *
0006  * S3C2410 Memory Control register definitions
0007  */
0008
0009 #ifndef __ARCH_ARM_MACH_S3C24XX_REGS_MEM_H
0010 #define __ARCH_ARM_MACH_S3C24XX_REGS_MEM_H __FILE__
0011
0012 #include "map-s3c.h"
0013
0014 #define S3C2410_MEMREG(x)       (S3C24XX_VA_MEMCTRL + (x))
0015
0016 #define S3C2410_BWSCON          S3C2410_MEMREG(0x00)
0017 #define S3C2410_BANKCON0        S3C2410_MEMREG(0x04)
0018 #define S3C2410_BANKCON1        S3C2410_MEMREG(0x08)
0019 #define S3C2410_BANKCON2        S3C2410_MEMREG(0x0C)
0020 #define S3C2410_BANKCON3        S3C2410_MEMREG(0x10)
0021 #define S3C2410_BANKCON4        S3C2410_MEMREG(0x14)
0022 #define S3C2410_BANKCON5        S3C2410_MEMREG(0x18)
0023 #define S3C2410_BANKCON6        S3C2410_MEMREG(0x1C)
0024 #define S3C2410_BANKCON7        S3C2410_MEMREG(0x20)
0025 #define S3C2410_REFRESH         S3C2410_MEMREG(0x24)
0026 #define S3C2410_BANKSIZE        S3C2410_MEMREG(0x28)
0027
0028 #define S3C2410_BWSCON_ST1      (1 << 7)
0029 #define S3C2410_BWSCON_ST2      (1 << 11)
0030 #define S3C2410_BWSCON_ST3      (1 << 15)
0031 #define S3C2410_BWSCON_ST4      (1 << 19)
0032 #define S3C2410_BWSCON_ST5      (1 << 23)
0033
0034 #define S3C2410_BWSCON_GET(_bwscon, _bank) (((_bwscon) >> ((_bank) * 4)) & 0xf)
0035
0036 #define S3C2410_BWSCON_WS       (1 << 2)
0037
0038 #define S3C2410_BANKCON_PMC16       (0x3)
0039
0040 #define S3C2410_BANKCON_Tacp_SHIFT  (2)
0041 #define S3C2410_BANKCON_Tcah_SHIFT  (4)
0042 #define S3C2410_BANKCON_Tcoh_SHIFT  (6)
0043 #define S3C2410_BANKCON_Tacc_SHIFT  (8)
0044 #define S3C2410_BANKCON_Tcos_SHIFT  (11)
0045 #define S3C2410_BANKCON_Tacs_SHIFT  (13)
0046
0047 #define S3C2410_BANKCON_SDRAM       (0x3 << 15)
0048
0049 #define S3C2410_REFRESH_SELF        (1 << 22)
0050
0051 #define S3C2410_BANKSIZE_MASK       (0x7 << 0)
0052
0053 #endif /* __ARCH_ARM_MACH_S3C24XX_REGS_MEM_H */