arm/mach-s3c/regs-clock-s3c24xx.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright (c) 2003-2006 Simtec Electronics <linux@simtec.co.uk>
0004  *  http://armlinux.simtec.co.uk/
0005  *
0006  * S3C2410 clock register definitions
0007  */
0008
0009 #ifndef __ASM_ARM_REGS_CLOCK
0010 #define __ASM_ARM_REGS_CLOCK
0011
0012 #include "map.h"
0013
0014 #define S3C2410_CLKREG(x) ((x) + S3C24XX_VA_CLKPWR)
0015
0016 #define S3C2410_PLLVAL(_m,_p,_s) ((_m) << 12 | ((_p) << 4) | ((_s)))
0017
0018 #define S3C2410_LOCKTIME    S3C2410_CLKREG(0x00)
0019 #define S3C2410_MPLLCON     S3C2410_CLKREG(0x04)
0020 #define S3C2410_UPLLCON     S3C2410_CLKREG(0x08)
0021 #define S3C2410_CLKCON      S3C2410_CLKREG(0x0C)
0022 #define S3C2410_CLKSLOW     S3C2410_CLKREG(0x10)
0023 #define S3C2410_CLKDIVN     S3C2410_CLKREG(0x14)
0024
0025 #define S3C2410_CLKCON_IDLE      (1<<2)
0026 #define S3C2410_CLKCON_POWER         (1<<3)
0027 #define S3C2410_CLKCON_NAND      (1<<4)
0028 #define S3C2410_CLKCON_LCDC      (1<<5)
0029 #define S3C2410_CLKCON_USBH      (1<<6)
0030 #define S3C2410_CLKCON_USBD      (1<<7)
0031 #define S3C2410_CLKCON_PWMT      (1<<8)
0032 #define S3C2410_CLKCON_SDI       (1<<9)
0033 #define S3C2410_CLKCON_UART0         (1<<10)
0034 #define S3C2410_CLKCON_UART1         (1<<11)
0035 #define S3C2410_CLKCON_UART2         (1<<12)
0036 #define S3C2410_CLKCON_GPIO      (1<<13)
0037 #define S3C2410_CLKCON_RTC       (1<<14)
0038 #define S3C2410_CLKCON_ADC       (1<<15)
0039 #define S3C2410_CLKCON_IIC       (1<<16)
0040 #define S3C2410_CLKCON_IIS       (1<<17)
0041 #define S3C2410_CLKCON_SPI       (1<<18)
0042
0043 #define S3C2410_CLKDIVN_PDIVN        (1<<0)
0044 #define S3C2410_CLKDIVN_HDIVN        (1<<1)
0045
0046 #define S3C2410_CLKSLOW_UCLK_OFF    (1<<7)
0047 #define S3C2410_CLKSLOW_MPLL_OFF    (1<<5)
0048 #define S3C2410_CLKSLOW_SLOW        (1<<4)
0049 #define S3C2410_CLKSLOW_SLOWVAL(x)  (x)
0050 #define S3C2410_CLKSLOW_GET_SLOWVAL(x)  ((x) & 7)
0051
0052 #if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442)
0053
0054 /* extra registers */
0055 #define S3C2440_CAMDIVN     S3C2410_CLKREG(0x18)
0056
0057 #define S3C2440_CLKCON_CAMERA        (1<<19)
0058 #define S3C2440_CLKCON_AC97          (1<<20)
0059
0060 #define S3C2440_CLKDIVN_PDIVN        (1<<0)
0061 #define S3C2440_CLKDIVN_HDIVN_MASK   (3<<1)
0062 #define S3C2440_CLKDIVN_HDIVN_1      (0<<1)
0063 #define S3C2440_CLKDIVN_HDIVN_2      (1<<1)
0064 #define S3C2440_CLKDIVN_HDIVN_4_8    (2<<1)
0065 #define S3C2440_CLKDIVN_HDIVN_3_6    (3<<1)
0066 #define S3C2440_CLKDIVN_UCLK         (1<<3)
0067
0068 #define S3C2440_CAMDIVN_CAMCLK_MASK  (0xf<<0)
0069 #define S3C2440_CAMDIVN_CAMCLK_SEL   (1<<4)
0070 #define S3C2440_CAMDIVN_HCLK3_HALF   (1<<8)
0071 #define S3C2440_CAMDIVN_HCLK4_HALF   (1<<9)
0072 #define S3C2440_CAMDIVN_DVSEN        (1<<12)
0073
0074 #define S3C2442_CAMDIVN_CAMCLK_DIV3  (1<<5)
0075
0076 #endif /* CONFIG_CPU_S3C2440 or CONFIG_CPU_S3C2442 */
0077
0078 #if defined(CONFIG_CPU_S3C2412)
0079
0080 #define S3C2412_OSCSET      S3C2410_CLKREG(0x18)
0081 #define S3C2412_CLKSRC      S3C2410_CLKREG(0x1C)
0082
0083 #define S3C2412_PLLCON_OFF      (1<<20)
0084
0085 #define S3C2412_CLKDIVN_PDIVN       (1<<2)
0086 #define S3C2412_CLKDIVN_HDIVN_MASK  (3<<0)
0087 #define S3C2412_CLKDIVN_ARMDIVN     (1<<3)
0088 #define S3C2412_CLKDIVN_DVSEN       (1<<4)
0089 #define S3C2412_CLKDIVN_HALFHCLK    (1<<5)
0090 #define S3C2412_CLKDIVN_USB48DIV    (1<<6)
0091 #define S3C2412_CLKDIVN_UARTDIV_MASK    (15<<8)
0092 #define S3C2412_CLKDIVN_UARTDIV_SHIFT   (8)
0093 #define S3C2412_CLKDIVN_I2SDIV_MASK (15<<12)
0094 #define S3C2412_CLKDIVN_I2SDIV_SHIFT    (12)
0095 #define S3C2412_CLKDIVN_CAMDIV_MASK (15<<16)
0096 #define S3C2412_CLKDIVN_CAMDIV_SHIFT    (16)
0097
0098 #define S3C2412_CLKCON_WDT      (1<<28)
0099 #define S3C2412_CLKCON_SPI      (1<<27)
0100 #define S3C2412_CLKCON_IIS      (1<<26)
0101 #define S3C2412_CLKCON_IIC      (1<<25)
0102 #define S3C2412_CLKCON_ADC      (1<<24)
0103 #define S3C2412_CLKCON_RTC      (1<<23)
0104 #define S3C2412_CLKCON_GPIO     (1<<22)
0105 #define S3C2412_CLKCON_UART2        (1<<21)
0106 #define S3C2412_CLKCON_UART1        (1<<20)
0107 #define S3C2412_CLKCON_UART0        (1<<19)
0108 #define S3C2412_CLKCON_SDI      (1<<18)
0109 #define S3C2412_CLKCON_PWMT     (1<<17)
0110 #define S3C2412_CLKCON_USBD     (1<<16)
0111 #define S3C2412_CLKCON_CAMCLK       (1<<15)
0112 #define S3C2412_CLKCON_UARTCLK      (1<<14)
0113 /* missing 13 */
0114 #define S3C2412_CLKCON_USB_HOST48   (1<<12)
0115 #define S3C2412_CLKCON_USB_DEV48    (1<<11)
0116 #define S3C2412_CLKCON_HCLKdiv2     (1<<10)
0117 #define S3C2412_CLKCON_HCLKx2       (1<<9)
0118 #define S3C2412_CLKCON_SDRAM        (1<<8)
0119 /* missing 7 */
0120 #define S3C2412_CLKCON_USBH     S3C2410_CLKCON_USBH
0121 #define S3C2412_CLKCON_LCDC     S3C2410_CLKCON_LCDC
0122 #define S3C2412_CLKCON_NAND     S3C2410_CLKCON_NAND
0123 #define S3C2412_CLKCON_DMA3     (1<<3)
0124 #define S3C2412_CLKCON_DMA2     (1<<2)
0125 #define S3C2412_CLKCON_DMA1     (1<<1)
0126 #define S3C2412_CLKCON_DMA0     (1<<0)
0127
0128 /* clock sourec controls */
0129
0130 #define S3C2412_CLKSRC_EXTCLKDIV_MASK       (7 << 0)
0131 #define S3C2412_CLKSRC_EXTCLKDIV_SHIFT      (0)
0132 #define S3C2412_CLKSRC_MDIVCLK_EXTCLKDIV    (1<<3)
0133 #define S3C2412_CLKSRC_MSYSCLK_MPLL     (1<<4)
0134 #define S3C2412_CLKSRC_USYSCLK_UPLL     (1<<5)
0135 #define S3C2412_CLKSRC_UARTCLK_MPLL     (1<<8)
0136 #define S3C2412_CLKSRC_I2SCLK_MPLL      (1<<9)
0137 #define S3C2412_CLKSRC_USBCLK_HCLK      (1<<10)
0138 #define S3C2412_CLKSRC_CAMCLK_HCLK      (1<<11)
0139 #define S3C2412_CLKSRC_UREFCLK_EXTCLK   (1<<12)
0140 #define S3C2412_CLKSRC_EREFCLK_EXTCLK   (1<<14)
0141
0142 #endif /* CONFIG_CPU_S3C2412 */
0143
0144 #define S3C2416_CLKDIV2     S3C2410_CLKREG(0x28)
0145
0146 #endif /* __ASM_ARM_REGS_CLOCK */