arm/mach-s3c/regs-adc.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright (c) 2004 Shannon Holland <holland@loser.net>
0004  *
0005  * S3C2410 ADC registers
0006  */
0007
0008 #ifndef __ASM_ARCH_REGS_ADC_H
0009 #define __ASM_ARCH_REGS_ADC_H "regs-adc.h"
0010
0011 #define S3C2410_ADCREG(x) (x)
0012
0013 #define S3C2410_ADCCON     S3C2410_ADCREG(0x00)
0014 #define S3C2410_ADCTSC     S3C2410_ADCREG(0x04)
0015 #define S3C2410_ADCDLY     S3C2410_ADCREG(0x08)
0016 #define S3C2410_ADCDAT0    S3C2410_ADCREG(0x0C)
0017 #define S3C2410_ADCDAT1    S3C2410_ADCREG(0x10)
0018 #define S3C64XX_ADCUPDN     S3C2410_ADCREG(0x14)
0019 #define S3C2443_ADCMUX      S3C2410_ADCREG(0x18)
0020 #define S3C64XX_ADCCLRINT   S3C2410_ADCREG(0x18)
0021 #define S5P_ADCMUX      S3C2410_ADCREG(0x1C)
0022 #define S3C64XX_ADCCLRINTPNDNUP S3C2410_ADCREG(0x20)
0023
0024
0025 /* ADCCON Register Bits */
0026 #define S3C64XX_ADCCON_RESSEL       (1<<16)
0027 #define S3C2410_ADCCON_ECFLG        (1<<15)
0028 #define S3C2410_ADCCON_PRSCEN       (1<<14)
0029 #define S3C2410_ADCCON_PRSCVL(x)    (((x)&0xFF)<<6)
0030 #define S3C2410_ADCCON_PRSCVLMASK   (0xFF<<6)
0031 #define S3C2410_ADCCON_SELMUX(x)    (((x)&0x7)<<3)
0032 #define S3C2410_ADCCON_MUXMASK      (0x7<<3)
0033 #define S3C2416_ADCCON_RESSEL       (1 << 3)
0034 #define S3C2410_ADCCON_STDBM        (1<<2)
0035 #define S3C2410_ADCCON_READ_START   (1<<1)
0036 #define S3C2410_ADCCON_ENABLE_START (1<<0)
0037 #define S3C2410_ADCCON_STARTMASK    (0x3<<0)
0038
0039
0040 /* ADCTSC Register Bits */
0041 #define S3C2443_ADCTSC_UD_SEN       (1 << 8)
0042 #define S3C2410_ADCTSC_YM_SEN       (1<<7)
0043 #define S3C2410_ADCTSC_YP_SEN       (1<<6)
0044 #define S3C2410_ADCTSC_XM_SEN       (1<<5)
0045 #define S3C2410_ADCTSC_XP_SEN       (1<<4)
0046 #define S3C2410_ADCTSC_PULL_UP_DISABLE  (1<<3)
0047 #define S3C2410_ADCTSC_AUTO_PST     (1<<2)
0048 #define S3C2410_ADCTSC_XY_PST(x)    (((x)&0x3)<<0)
0049
0050 /* ADCDAT0 Bits */
0051 #define S3C2410_ADCDAT0_UPDOWN      (1<<15)
0052 #define S3C2410_ADCDAT0_AUTO_PST    (1<<14)
0053 #define S3C2410_ADCDAT0_XY_PST      (0x3<<12)
0054 #define S3C2410_ADCDAT0_XPDATA_MASK (0x03FF)
0055
0056 /* ADCDAT1 Bits */
0057 #define S3C2410_ADCDAT1_UPDOWN      (1<<15)
0058 #define S3C2410_ADCDAT1_AUTO_PST    (1<<14)
0059 #define S3C2410_ADCDAT1_XY_PST      (0x3<<12)
0060 #define S3C2410_ADCDAT1_YPDATA_MASK (0x03FF)
0061
0062 #endif /* __ASM_ARCH_REGS_ADC_H */
0063
0064