arm/mach-s3c/pm-s3c64xx.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 //
0003 // Copyright 2008 Openmoko, Inc.
0004 // Copyright 2008 Simtec Electronics
0005 //  Ben Dooks <ben@simtec.co.uk>
0006 //  http://armlinux.simtec.co.uk/
0007 //
0008 // S3C64XX CPU PM support.
0009
0010 #include <linux/init.h>
0011 #include <linux/suspend.h>
0012 #include <linux/serial_core.h>
0013 #include <linux/io.h>
0014 #include <linux/gpio.h>
0015 #include <linux/pm_domain.h>
0016
0017 #include "map.h"
0018 #include "irqs.h"
0019
0020 #include "cpu.h"
0021 #include "devs.h"
0022 #include "pm.h"
0023 #include "wakeup-mask.h"
0024
0025 #include "regs-gpio.h"
0026 #include "regs-clock.h"
0027 #include "gpio-samsung.h"
0028
0029 #include "regs-gpio-memport-s3c64xx.h"
0030 #include "regs-modem-s3c64xx.h"
0031 #include "regs-sys-s3c64xx.h"
0032 #include "regs-syscon-power-s3c64xx.h"
0033
0034 struct s3c64xx_pm_domain {
0035     char *const name;
0036     u32 ena;
0037     u32 pwr_stat;
0038     struct generic_pm_domain pd;
0039 };
0040
0041 static int s3c64xx_pd_off(struct generic_pm_domain *domain)
0042 {
0043     struct s3c64xx_pm_domain *pd;
0044     u32 val;
0045
0046     pd = container_of(domain, struct s3c64xx_pm_domain, pd);
0047
0048     val = __raw_readl(S3C64XX_NORMAL_CFG);
0049     val &= ~(pd->ena);
0050     __raw_writel(val, S3C64XX_NORMAL_CFG);
0051
0052     return 0;
0053 }
0054
0055 static int s3c64xx_pd_on(struct generic_pm_domain *domain)
0056 {
0057     struct s3c64xx_pm_domain *pd;
0058     u32 val;
0059     long retry = 1000000L;
0060
0061     pd = container_of(domain, struct s3c64xx_pm_domain, pd);
0062
0063     val = __raw_readl(S3C64XX_NORMAL_CFG);
0064     val |= pd->ena;
0065     __raw_writel(val, S3C64XX_NORMAL_CFG);
0066
0067     /* Not all domains provide power status readback */
0068     if (pd->pwr_stat) {
0069         do {
0070             cpu_relax();
0071             if (__raw_readl(S3C64XX_BLK_PWR_STAT) & pd->pwr_stat)
0072                 break;
0073         } while (retry--);
0074
0075         if (!retry) {
0076             pr_err("Failed to start domain %s\n", pd->name);
0077             return -EBUSY;
0078         }
0079     }
0080
0081     return 0;
0082 }
0083
0084 static struct s3c64xx_pm_domain s3c64xx_pm_irom = {
0085     .name = "IROM",
0086     .ena = S3C64XX_NORMALCFG_IROM_ON,
0087     .pd = {
0088         .power_off = s3c64xx_pd_off,
0089         .power_on = s3c64xx_pd_on,
0090     },
0091 };
0092
0093 static struct s3c64xx_pm_domain s3c64xx_pm_etm = {
0094     .name = "ETM",
0095     .ena = S3C64XX_NORMALCFG_DOMAIN_ETM_ON,
0096     .pwr_stat = S3C64XX_BLKPWRSTAT_ETM,
0097     .pd = {
0098         .power_off = s3c64xx_pd_off,
0099         .power_on = s3c64xx_pd_on,
0100     },
0101 };
0102
0103 static struct s3c64xx_pm_domain s3c64xx_pm_s = {
0104     .name = "S",
0105     .ena = S3C64XX_NORMALCFG_DOMAIN_S_ON,
0106     .pwr_stat = S3C64XX_BLKPWRSTAT_S,
0107     .pd = {
0108         .power_off = s3c64xx_pd_off,
0109         .power_on = s3c64xx_pd_on,
0110     },
0111 };
0112
0113 static struct s3c64xx_pm_domain s3c64xx_pm_f = {
0114     .name = "F",
0115     .ena = S3C64XX_NORMALCFG_DOMAIN_F_ON,
0116     .pwr_stat = S3C64XX_BLKPWRSTAT_F,
0117     .pd = {
0118         .power_off = s3c64xx_pd_off,
0119         .power_on = s3c64xx_pd_on,
0120     },
0121 };
0122
0123 static struct s3c64xx_pm_domain s3c64xx_pm_p = {
0124     .name = "P",
0125     .ena = S3C64XX_NORMALCFG_DOMAIN_P_ON,
0126     .pwr_stat = S3C64XX_BLKPWRSTAT_P,
0127     .pd = {
0128         .power_off = s3c64xx_pd_off,
0129         .power_on = s3c64xx_pd_on,
0130     },
0131 };
0132
0133 static struct s3c64xx_pm_domain s3c64xx_pm_i = {
0134     .name = "I",
0135     .ena = S3C64XX_NORMALCFG_DOMAIN_I_ON,
0136     .pwr_stat = S3C64XX_BLKPWRSTAT_I,
0137     .pd = {
0138         .power_off = s3c64xx_pd_off,
0139         .power_on = s3c64xx_pd_on,
0140     },
0141 };
0142
0143 static struct s3c64xx_pm_domain s3c64xx_pm_g = {
0144     .name = "G",
0145     .ena = S3C64XX_NORMALCFG_DOMAIN_G_ON,
0146     .pd = {
0147         .power_off = s3c64xx_pd_off,
0148         .power_on = s3c64xx_pd_on,
0149     },
0150 };
0151
0152 static struct s3c64xx_pm_domain s3c64xx_pm_v = {
0153     .name = "V",
0154     .ena = S3C64XX_NORMALCFG_DOMAIN_V_ON,
0155     .pwr_stat = S3C64XX_BLKPWRSTAT_V,
0156     .pd = {
0157         .power_off = s3c64xx_pd_off,
0158         .power_on = s3c64xx_pd_on,
0159     },
0160 };
0161
0162 static struct s3c64xx_pm_domain *s3c64xx_always_on_pm_domains[] = {
0163     &s3c64xx_pm_irom,
0164 };
0165
0166 static struct s3c64xx_pm_domain *s3c64xx_pm_domains[] = {
0167     &s3c64xx_pm_etm,
0168     &s3c64xx_pm_g,
0169     &s3c64xx_pm_v,
0170     &s3c64xx_pm_i,
0171     &s3c64xx_pm_p,
0172     &s3c64xx_pm_s,
0173     &s3c64xx_pm_f,
0174 };
0175
0176 #ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK
0177 void s3c_pm_debug_smdkled(u32 set, u32 clear)
0178 {
0179     unsigned long flags;
0180     int i;
0181
0182     local_irq_save(flags);
0183     for (i = 0; i < 4; i++) {
0184         if (clear & (1 << i))
0185             gpio_set_value(S3C64XX_GPN(12 + i), 0);
0186         if (set & (1 << i))
0187             gpio_set_value(S3C64XX_GPN(12 + i), 1);
0188     }
0189     local_irq_restore(flags);
0190 }
0191 #endif
0192
0193 #ifdef CONFIG_PM_SLEEP
0194 static struct sleep_save core_save[] = {
0195     SAVE_ITEM(S3C64XX_MEM0DRVCON),
0196     SAVE_ITEM(S3C64XX_MEM1DRVCON),
0197 };
0198
0199 static struct sleep_save misc_save[] = {
0200     SAVE_ITEM(S3C64XX_AHB_CON0),
0201     SAVE_ITEM(S3C64XX_AHB_CON1),
0202     SAVE_ITEM(S3C64XX_AHB_CON2),
0203
0204     SAVE_ITEM(S3C64XX_SPCON),
0205
0206     SAVE_ITEM(S3C64XX_MEM0CONSTOP),
0207     SAVE_ITEM(S3C64XX_MEM1CONSTOP),
0208     SAVE_ITEM(S3C64XX_MEM0CONSLP0),
0209     SAVE_ITEM(S3C64XX_MEM0CONSLP1),
0210     SAVE_ITEM(S3C64XX_MEM1CONSLP),
0211
0212     SAVE_ITEM(S3C64XX_SDMA_SEL),
0213     SAVE_ITEM(S3C64XX_MODEM_MIFPCON),
0214
0215     SAVE_ITEM(S3C64XX_NORMAL_CFG),
0216 };
0217
0218 void s3c_pm_configure_extint(void)
0219 {
0220     __raw_writel(s3c_irqwake_eintmask, S3C64XX_EINT_MASK);
0221 }
0222
0223 void s3c_pm_restore_core(void)
0224 {
0225     __raw_writel(0, S3C64XX_EINT_MASK);
0226
0227     s3c_pm_debug_smdkled(1 << 2, 0);
0228
0229     s3c_pm_do_restore_core(core_save, ARRAY_SIZE(core_save));
0230     s3c_pm_do_restore(misc_save, ARRAY_SIZE(misc_save));
0231 }
0232
0233 void s3c_pm_save_core(void)
0234 {
0235     s3c_pm_do_save(misc_save, ARRAY_SIZE(misc_save));
0236     s3c_pm_do_save(core_save, ARRAY_SIZE(core_save));
0237 }
0238 #endif
0239
0240 /* since both s3c6400 and s3c6410 share the same sleep pm calls, we
0241  * put the per-cpu code in here until any new cpu comes along and changes
0242  * this.
0243  */
0244
0245 static int s3c64xx_cpu_suspend(unsigned long arg)
0246 {
0247     unsigned long tmp;
0248
0249     /* set our standby method to sleep */
0250
0251     tmp = __raw_readl(S3C64XX_PWR_CFG);
0252     tmp &= ~S3C64XX_PWRCFG_CFG_WFI_MASK;
0253     tmp |= S3C64XX_PWRCFG_CFG_WFI_SLEEP;
0254     __raw_writel(tmp, S3C64XX_PWR_CFG);
0255
0256     /* clear any old wakeup */
0257
0258     __raw_writel(__raw_readl(S3C64XX_WAKEUP_STAT),
0259              S3C64XX_WAKEUP_STAT);
0260
0261     /* set the LED state to 0110 over sleep */
0262     s3c_pm_debug_smdkled(3 << 1, 0xf);
0263
0264     /* issue the standby signal into the pm unit. Note, we
0265      * issue a write-buffer drain just in case */
0266
0267     tmp = 0;
0268
0269     asm("b 1f\n\t"
0270         ".align 5\n\t"
0271         "1:\n\t"
0272         "mcr p15, 0, %0, c7, c10, 5\n\t"
0273         "mcr p15, 0, %0, c7, c10, 4\n\t"
0274         "mcr p15, 0, %0, c7, c0, 4" :: "r" (tmp));
0275
0276     /* we should never get past here */
0277
0278     pr_info("Failed to suspend the system\n");
0279     return 1; /* Aborting suspend */
0280 }
0281
0282 /* mapping of interrupts to parts of the wakeup mask */
0283 static const struct samsung_wakeup_mask wake_irqs[] = {
0284     { .irq = IRQ_RTC_ALARM, .bit = S3C64XX_PWRCFG_RTC_ALARM_DISABLE, },
0285     { .irq = IRQ_RTC_TIC,   .bit = S3C64XX_PWRCFG_RTC_TICK_DISABLE, },
0286     { .irq = IRQ_PENDN, .bit = S3C64XX_PWRCFG_TS_DISABLE, },
0287     { .irq = IRQ_HSMMC0,    .bit = S3C64XX_PWRCFG_MMC0_DISABLE, },
0288     { .irq = IRQ_HSMMC1,    .bit = S3C64XX_PWRCFG_MMC1_DISABLE, },
0289     { .irq = IRQ_HSMMC2,    .bit = S3C64XX_PWRCFG_MMC2_DISABLE, },
0290     { .irq = NO_WAKEUP_IRQ, .bit = S3C64XX_PWRCFG_BATF_DISABLE},
0291     { .irq = NO_WAKEUP_IRQ, .bit = S3C64XX_PWRCFG_MSM_DISABLE },
0292     { .irq = NO_WAKEUP_IRQ, .bit = S3C64XX_PWRCFG_HSI_DISABLE },
0293     { .irq = NO_WAKEUP_IRQ, .bit = S3C64XX_PWRCFG_MSM_DISABLE },
0294 };
0295
0296 static void s3c64xx_pm_prepare(void)
0297 {
0298     samsung_sync_wakemask(S3C64XX_PWR_CFG,
0299                   wake_irqs, ARRAY_SIZE(wake_irqs));
0300
0301     /* store address of resume. */
0302     __raw_writel(__pa_symbol(s3c_cpu_resume), S3C64XX_INFORM0);
0303
0304     /* ensure previous wakeup state is cleared before sleeping */
0305     __raw_writel(__raw_readl(S3C64XX_WAKEUP_STAT), S3C64XX_WAKEUP_STAT);
0306 }
0307
0308 #ifdef CONFIG_SAMSUNG_PM_DEBUG
0309 void s3c_pm_arch_update_uart(void __iomem *regs, struct pm_uart_save *save)
0310 {
0311     u32 ucon;
0312     u32 ucon_clk
0313     u32 save_clk;
0314     u32 new_ucon;
0315     u32 delta;
0316
0317     if (!soc_is_s3c64xx())
0318         return;
0319
0320     ucon = __raw_readl(regs + S3C2410_UCON);
0321     ucon_clk = ucon & S3C6400_UCON_CLKMASK;
0322     sav_clk = save->ucon & S3C6400_UCON_CLKMASK;
0323
0324     /* S3C64XX UART blocks only support level interrupts, so ensure that
0325      * when we restore unused UART blocks we force the level interrupt
0326      * settings. */
0327     save->ucon |= S3C2410_UCON_TXILEVEL | S3C2410_UCON_RXILEVEL;
0328
0329     /* We have a constraint on changing the clock type of the UART
0330      * between UCLKx and PCLK, so ensure that when we restore UCON
0331      * that the CLK field is correctly modified if the bootloader
0332      * has changed anything.
0333      */
0334     if (ucon_clk != save_clk) {
0335         new_ucon = save->ucon;
0336         delta = ucon_clk ^ save_clk;
0337
0338         /* change from UCLKx => wrong PCLK,
0339          * either UCLK can be tested for by a bit-test
0340          * with UCLK0 */
0341         if (ucon_clk & S3C6400_UCON_UCLK0 &&
0342             !(save_clk & S3C6400_UCON_UCLK0) &&
0343             delta & S3C6400_UCON_PCLK2) {
0344             new_ucon &= ~S3C6400_UCON_UCLK0;
0345         } else if (delta == S3C6400_UCON_PCLK2) {
0346             /* as an precaution, don't change from
0347              * PCLK2 => PCLK or vice-versa */
0348             new_ucon ^= S3C6400_UCON_PCLK2;
0349         }
0350
0351         S3C_PMDBG("ucon change %04x => %04x (save=%04x)\n",
0352               ucon, new_ucon, save->ucon);
0353         save->ucon = new_ucon;
0354     }
0355 }
0356 #endif
0357
0358 int __init s3c64xx_pm_init(void)
0359 {
0360     int i;
0361
0362     s3c_pm_init();
0363
0364     for (i = 0; i < ARRAY_SIZE(s3c64xx_always_on_pm_domains); i++)
0365         pm_genpd_init(&s3c64xx_always_on_pm_domains[i]->pd,
0366                   &pm_domain_always_on_gov, false);
0367
0368     for (i = 0; i < ARRAY_SIZE(s3c64xx_pm_domains); i++)
0369         pm_genpd_init(&s3c64xx_pm_domains[i]->pd, NULL, false);
0370
0371 #ifdef CONFIG_S3C_DEV_FB
0372     if (dev_get_platdata(&s3c_device_fb.dev))
0373         pm_genpd_add_device(&s3c64xx_pm_f.pd, &s3c_device_fb.dev);
0374 #endif
0375
0376     return 0;
0377 }
0378
0379 static __init int s3c64xx_pm_initcall(void)
0380 {
0381     if (!soc_is_s3c64xx())
0382         return 0;
0383
0384     pm_cpu_prep = s3c64xx_pm_prepare;
0385     pm_cpu_sleep = s3c64xx_cpu_suspend;
0386
0387 #ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK
0388     gpio_request(S3C64XX_GPN(12), "DEBUG_LED0");
0389     gpio_request(S3C64XX_GPN(13), "DEBUG_LED1");
0390     gpio_request(S3C64XX_GPN(14), "DEBUG_LED2");
0391     gpio_request(S3C64XX_GPN(15), "DEBUG_LED3");
0392     gpio_direction_output(S3C64XX_GPN(12), 0);
0393     gpio_direction_output(S3C64XX_GPN(13), 0);
0394     gpio_direction_output(S3C64XX_GPN(14), 0);
0395     gpio_direction_output(S3C64XX_GPN(15), 0);
0396 #endif
0397
0398     return 0;
0399 }
0400 arch_initcall(s3c64xx_pm_initcall);