arm/mach-s3c/pm-s3c2410.c

0001 // SPDX-License-Identifier: GPL-2.0+
0002 //
0003 // Copyright (c) 2006 Simtec Electronics
0004 //  Ben Dooks <ben@simtec.co.uk>
0005 //
0006 // S3C2410 (and compatible) Power Manager (Suspend-To-RAM) support
0007
0008 #include <linux/init.h>
0009 #include <linux/suspend.h>
0010 #include <linux/errno.h>
0011 #include <linux/time.h>
0012 #include <linux/device.h>
0013 #include <linux/syscore_ops.h>
0014 #include <linux/gpio.h>
0015 #include <linux/io.h>
0016
0017 #include <asm/mach-types.h>
0018
0019 #include "regs-gpio.h"
0020 #include "gpio-samsung.h"
0021
0022 #include "gpio-cfg.h"
0023 #include "cpu.h"
0024 #include "pm.h"
0025
0026 #include "h1940.h"
0027
0028 static void s3c2410_pm_prepare(void)
0029 {
0030     /* ensure at least GSTATUS3 has the resume address */
0031
0032     __raw_writel(__pa_symbol(s3c_cpu_resume), S3C2410_GSTATUS3);
0033
0034     S3C_PMDBG("GSTATUS3 0x%08x\n", __raw_readl(S3C2410_GSTATUS3));
0035     S3C_PMDBG("GSTATUS4 0x%08x\n", __raw_readl(S3C2410_GSTATUS4));
0036
0037     if (machine_is_h1940()) {
0038         void *base = phys_to_virt(H1940_SUSPEND_CHECK);
0039         unsigned long ptr;
0040         unsigned long calc = 0;
0041
0042         /* generate check for the bootloader to check on resume */
0043
0044         for (ptr = 0; ptr < 0x40000; ptr += 0x400)
0045             calc += __raw_readl(base+ptr);
0046
0047         __raw_writel(calc, phys_to_virt(H1940_SUSPEND_CHECKSUM));
0048     }
0049
0050     /* RX3715 and RX1950 use similar to H1940 code and the
0051      * same offsets for resume and checksum pointers */
0052
0053     if (machine_is_rx3715() || machine_is_rx1950()) {
0054         void *base = phys_to_virt(H1940_SUSPEND_CHECK);
0055         unsigned long ptr;
0056         unsigned long calc = 0;
0057
0058         /* generate check for the bootloader to check on resume */
0059
0060         for (ptr = 0; ptr < 0x40000; ptr += 0x4)
0061             calc += __raw_readl(base+ptr);
0062
0063         __raw_writel(calc, phys_to_virt(H1940_SUSPEND_CHECKSUM));
0064     }
0065
0066     if (machine_is_aml_m5900()) {
0067         gpio_request_one(S3C2410_GPF(2), GPIOF_OUT_INIT_HIGH, NULL);
0068         gpio_free(S3C2410_GPF(2));
0069     }
0070
0071     if (machine_is_rx1950()) {
0072         /* According to S3C2442 user's manual, page 7-17,
0073          * when the system is operating in NAND boot mode,
0074          * the hardware pin configuration - EINT[23:21] –
0075          * must be set as input for starting up after
0076          * wakeup from sleep mode
0077          */
0078         s3c_gpio_cfgpin(S3C2410_GPG(13), S3C2410_GPIO_INPUT);
0079         s3c_gpio_cfgpin(S3C2410_GPG(14), S3C2410_GPIO_INPUT);
0080         s3c_gpio_cfgpin(S3C2410_GPG(15), S3C2410_GPIO_INPUT);
0081     }
0082 }
0083
0084 static void s3c2410_pm_resume(void)
0085 {
0086     unsigned long tmp;
0087
0088     /* unset the return-from-sleep flag, to ensure reset */
0089
0090     tmp = __raw_readl(S3C2410_GSTATUS2);
0091     tmp &= S3C2410_GSTATUS2_OFFRESET;
0092     __raw_writel(tmp, S3C2410_GSTATUS2);
0093
0094     if (machine_is_aml_m5900()) {
0095         gpio_request_one(S3C2410_GPF(2), GPIOF_OUT_INIT_LOW, NULL);
0096         gpio_free(S3C2410_GPF(2));
0097     }
0098 }
0099
0100 struct syscore_ops s3c2410_pm_syscore_ops = {
0101     .resume     = s3c2410_pm_resume,
0102 };
0103
0104 static int s3c2410_pm_add(struct device *dev, struct subsys_interface *sif)
0105 {
0106     pm_cpu_prep = s3c2410_pm_prepare;
0107     pm_cpu_sleep = s3c2410_cpu_suspend;
0108
0109     return 0;
0110 }
0111
0112 #if defined(CONFIG_CPU_S3C2410)
0113 static struct subsys_interface s3c2410_pm_interface = {
0114     .name       = "s3c2410_pm",
0115     .subsys     = &s3c2410_subsys,
0116     .add_dev    = s3c2410_pm_add,
0117 };
0118
0119 /* register ourselves */
0120
0121 static int __init s3c2410_pm_drvinit(void)
0122 {
0123     return subsys_interface_register(&s3c2410_pm_interface);
0124 }
0125
0126 arch_initcall(s3c2410_pm_drvinit);
0127
0128 static struct subsys_interface s3c2410a_pm_interface = {
0129     .name       = "s3c2410a_pm",
0130     .subsys     = &s3c2410a_subsys,
0131     .add_dev    = s3c2410_pm_add,
0132 };
0133
0134 static int __init s3c2410a_pm_drvinit(void)
0135 {
0136     return subsys_interface_register(&s3c2410a_pm_interface);
0137 }
0138
0139 arch_initcall(s3c2410a_pm_drvinit);
0140 #endif
0141
0142 #if defined(CONFIG_CPU_S3C2440)
0143 static struct subsys_interface s3c2440_pm_interface = {
0144     .name       = "s3c2440_pm",
0145     .subsys     = &s3c2440_subsys,
0146     .add_dev    = s3c2410_pm_add,
0147 };
0148
0149 static int __init s3c2440_pm_drvinit(void)
0150 {
0151     return subsys_interface_register(&s3c2440_pm_interface);
0152 }
0153
0154 arch_initcall(s3c2440_pm_drvinit);
0155 #endif
0156
0157 #if defined(CONFIG_CPU_S3C2442)
0158 static struct subsys_interface s3c2442_pm_interface = {
0159     .name       = "s3c2442_pm",
0160     .subsys     = &s3c2442_subsys,
0161     .add_dev    = s3c2410_pm_add,
0162 };
0163
0164 static int __init s3c2442_pm_drvinit(void)
0165 {
0166     return subsys_interface_register(&s3c2442_pm_interface);
0167 }
0168
0169 arch_initcall(s3c2442_pm_drvinit);
0170 #endif