arm/mach-s3c/pll-s3c2440-16934400.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 //
0003 // Copyright (c) 2006-2008 Simtec Electronics
0004 //  http://armlinux.simtec.co.uk/
0005 //  Ben Dooks <ben@simtec.co.uk>
0006 //  Vincent Sanders <vince@arm.linux.org.uk>
0007 //
0008 // S3C2440/S3C2442 CPU PLL tables (16.93444MHz Crystal)
0009
0010 #include <linux/types.h>
0011 #include <linux/kernel.h>
0012 #include <linux/device.h>
0013 #include <linux/clk.h>
0014 #include <linux/err.h>
0015
0016 #include <linux/soc/samsung/s3c-cpufreq-core.h>
0017 #include <linux/soc/samsung/s3c-pm.h>
0018
0019 /* This array should be sorted in ascending order of the frequencies */
0020 static struct cpufreq_frequency_table s3c2440_plls_169344[] = {
0021     { .frequency = 78019200,    .driver_data = PLLVAL(121, 5, 3),   },  /* FVco 624.153600 */
0022     { .frequency = 84067200,    .driver_data = PLLVAL(131, 5, 3),   },  /* FVco 672.537600 */
0023     { .frequency = 90115200,    .driver_data = PLLVAL(141, 5, 3),   },  /* FVco 720.921600 */
0024     { .frequency = 96163200,    .driver_data = PLLVAL(151, 5, 3),   },  /* FVco 769.305600 */
0025     { .frequency = 102135600,   .driver_data = PLLVAL(185, 6, 3),   },  /* FVco 817.084800 */
0026     { .frequency = 108259200,   .driver_data = PLLVAL(171, 5, 3),   },  /* FVco 866.073600 */
0027     { .frequency = 114307200,   .driver_data = PLLVAL(127, 3, 3),   },  /* FVco 914.457600 */
0028     { .frequency = 120234240,   .driver_data = PLLVAL(134, 3, 3),   },  /* FVco 961.873920 */
0029     { .frequency = 126161280,   .driver_data = PLLVAL(141, 3, 3),   },  /* FVco 1009.290240 */
0030     { .frequency = 132088320,   .driver_data = PLLVAL(148, 3, 3),   },  /* FVco 1056.706560 */
0031     { .frequency = 138015360,   .driver_data = PLLVAL(155, 3, 3),   },  /* FVco 1104.122880 */
0032     { .frequency = 144789120,   .driver_data = PLLVAL(163, 3, 3),   },  /* FVco 1158.312960 */
0033     { .frequency = 150100363,   .driver_data = PLLVAL(187, 9, 2),   },  /* FVco 600.401454 */
0034     { .frequency = 156038400,   .driver_data = PLLVAL(121, 5, 2),   },  /* FVco 624.153600 */
0035     { .frequency = 162086400,   .driver_data = PLLVAL(126, 5, 2),   },  /* FVco 648.345600 */
0036     { .frequency = 168134400,   .driver_data = PLLVAL(131, 5, 2),   },  /* FVco 672.537600 */
0037     { .frequency = 174048000,   .driver_data = PLLVAL(177, 7, 2),   },  /* FVco 696.192000 */
0038     { .frequency = 180230400,   .driver_data = PLLVAL(141, 5, 2),   },  /* FVco 720.921600 */
0039     { .frequency = 186278400,   .driver_data = PLLVAL(124, 4, 2),   },  /* FVco 745.113600 */
0040     { .frequency = 192326400,   .driver_data = PLLVAL(151, 5, 2),   },  /* FVco 769.305600 */
0041     { .frequency = 198132480,   .driver_data = PLLVAL(109, 3, 2),   },  /* FVco 792.529920 */
0042     { .frequency = 204271200,   .driver_data = PLLVAL(185, 6, 2),   },  /* FVco 817.084800 */
0043     { .frequency = 210268800,   .driver_data = PLLVAL(141, 4, 2),   },  /* FVco 841.075200 */
0044     { .frequency = 216518400,   .driver_data = PLLVAL(171, 5, 2),   },  /* FVco 866.073600 */
0045     { .frequency = 222264000,   .driver_data = PLLVAL(97, 2, 2),    },  /* FVco 889.056000 */
0046     { .frequency = 228614400,   .driver_data = PLLVAL(127, 3, 2),   },  /* FVco 914.457600 */
0047     { .frequency = 234259200,   .driver_data = PLLVAL(158, 4, 2),   },  /* FVco 937.036800 */
0048     { .frequency = 240468480,   .driver_data = PLLVAL(134, 3, 2),   },  /* FVco 961.873920 */
0049     { .frequency = 246960000,   .driver_data = PLLVAL(167, 4, 2),   },  /* FVco 987.840000 */
0050     { .frequency = 252322560,   .driver_data = PLLVAL(141, 3, 2),   },  /* FVco 1009.290240 */
0051     { .frequency = 258249600,   .driver_data = PLLVAL(114, 2, 2),   },  /* FVco 1032.998400 */
0052     { .frequency = 264176640,   .driver_data = PLLVAL(148, 3, 2),   },  /* FVco 1056.706560 */
0053     { .frequency = 270950400,   .driver_data = PLLVAL(120, 2, 2),   },  /* FVco 1083.801600 */
0054     { .frequency = 276030720,   .driver_data = PLLVAL(155, 3, 2),   },  /* FVco 1104.122880 */
0055     { .frequency = 282240000,   .driver_data = PLLVAL(92, 1, 2),    },  /* FVco 1128.960000 */
0056     { .frequency = 289578240,   .driver_data = PLLVAL(163, 3, 2),   },  /* FVco 1158.312960 */
0057     { .frequency = 294235200,   .driver_data = PLLVAL(131, 2, 2),   },  /* FVco 1176.940800 */
0058     { .frequency = 300200727,   .driver_data = PLLVAL(187, 9, 1),   },  /* FVco 600.401454 */
0059     { .frequency = 306358690,   .driver_data = PLLVAL(191, 9, 1),   },  /* FVco 612.717380 */
0060     { .frequency = 312076800,   .driver_data = PLLVAL(121, 5, 1),   },  /* FVco 624.153600 */
0061     { .frequency = 318366720,   .driver_data = PLLVAL(86, 3, 1),    },  /* FVco 636.733440 */
0062     { .frequency = 324172800,   .driver_data = PLLVAL(126, 5, 1),   },  /* FVco 648.345600 */
0063     { .frequency = 330220800,   .driver_data = PLLVAL(109, 4, 1),   },  /* FVco 660.441600 */
0064     { .frequency = 336268800,   .driver_data = PLLVAL(131, 5, 1),   },  /* FVco 672.537600 */
0065     { .frequency = 342074880,   .driver_data = PLLVAL(93, 3, 1),    },  /* FVco 684.149760 */
0066     { .frequency = 348096000,   .driver_data = PLLVAL(177, 7, 1),   },  /* FVco 696.192000 */
0067     { .frequency = 355622400,   .driver_data = PLLVAL(118, 4, 1),   },  /* FVco 711.244800 */
0068     { .frequency = 360460800,   .driver_data = PLLVAL(141, 5, 1),   },  /* FVco 720.921600 */
0069     { .frequency = 366206400,   .driver_data = PLLVAL(165, 6, 1),   },  /* FVco 732.412800 */
0070     { .frequency = 372556800,   .driver_data = PLLVAL(124, 4, 1),   },  /* FVco 745.113600 */
0071     { .frequency = 378201600,   .driver_data = PLLVAL(126, 4, 1),   },  /* FVco 756.403200 */
0072     { .frequency = 384652800,   .driver_data = PLLVAL(151, 5, 1),   },  /* FVco 769.305600 */
0073     { .frequency = 391608000,   .driver_data = PLLVAL(177, 6, 1),   },  /* FVco 783.216000 */
0074     { .frequency = 396264960,   .driver_data = PLLVAL(109, 3, 1),   },  /* FVco 792.529920 */
0075     { .frequency = 402192000,   .driver_data = PLLVAL(87, 2, 1),    },  /* FVco 804.384000 */
0076 };
0077
0078 static int s3c2440_plls169344_add(struct device *dev,
0079                   struct subsys_interface *sif)
0080 {
0081     struct clk *xtal_clk;
0082     unsigned long xtal;
0083
0084     xtal_clk = clk_get(NULL, "xtal");
0085     if (IS_ERR(xtal_clk))
0086         return PTR_ERR(xtal_clk);
0087
0088     xtal = clk_get_rate(xtal_clk);
0089     clk_put(xtal_clk);
0090
0091     if (xtal == 169344000) {
0092         printk(KERN_INFO "Using PLL table for 16.9344MHz crystal\n");
0093         return s3c_plltab_register(s3c2440_plls_169344,
0094                        ARRAY_SIZE(s3c2440_plls_169344));
0095     }
0096
0097     return 0;
0098 }
0099
0100 static struct subsys_interface s3c2440_plls169344_interface = {
0101     .name       = "s3c2440_plls169344",
0102     .subsys     = &s3c2440_subsys,
0103     .add_dev    = s3c2440_plls169344_add,
0104 };
0105
0106 static int __init s3c2440_pll_16934400(void)
0107 {
0108     return subsys_interface_register(&s3c2440_plls169344_interface);
0109 }
0110 arch_initcall(s3c2440_pll_16934400);
0111
0112 static struct subsys_interface s3c2442_plls169344_interface = {
0113     .name       = "s3c2442_plls169344",
0114     .subsys     = &s3c2442_subsys,
0115     .add_dev    = s3c2440_plls169344_add,
0116 };
0117
0118 static int __init s3c2442_pll_16934400(void)
0119 {
0120     return subsys_interface_register(&s3c2442_plls169344_interface);
0121 }
0122 arch_initcall(s3c2442_pll_16934400);