arm/mach-s3c/pll-s3c2440-12000000.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 //
0003 // Copyright (c) 2006-2007 Simtec Electronics
0004 //  http://armlinux.simtec.co.uk/
0005 //  Ben Dooks <ben@simtec.co.uk>
0006 //  Vincent Sanders <vince@arm.linux.org.uk>
0007 //
0008 // S3C2440/S3C2442 CPU PLL tables (12MHz Crystal)
0009
0010 #include <linux/types.h>
0011 #include <linux/kernel.h>
0012 #include <linux/device.h>
0013 #include <linux/clk.h>
0014 #include <linux/err.h>
0015
0016 #include <linux/soc/samsung/s3c-cpufreq-core.h>
0017 #include <linux/soc/samsung/s3c-pm.h>
0018
0019 /* This array should be sorted in ascending order of the frequencies */
0020 static struct cpufreq_frequency_table s3c2440_plls_12[] = {
0021     { .frequency = 75000000,    .driver_data = PLLVAL(0x75, 3, 3),  },  /* FVco 600.000000 */
0022     { .frequency = 80000000,    .driver_data = PLLVAL(0x98, 4, 3),  },  /* FVco 640.000000 */
0023     { .frequency = 90000000,    .driver_data = PLLVAL(0x70, 2, 3),  },  /* FVco 720.000000 */
0024     { .frequency = 100000000,   .driver_data = PLLVAL(0x5c, 1, 3),  },  /* FVco 800.000000 */
0025     { .frequency = 110000000,   .driver_data = PLLVAL(0x66, 1, 3),  },  /* FVco 880.000000 */
0026     { .frequency = 120000000,   .driver_data = PLLVAL(0x70, 1, 3),  },  /* FVco 960.000000 */
0027     { .frequency = 150000000,   .driver_data = PLLVAL(0x75, 3, 2),  },  /* FVco 600.000000 */
0028     { .frequency = 160000000,   .driver_data = PLLVAL(0x98, 4, 2),  },  /* FVco 640.000000 */
0029     { .frequency = 170000000,   .driver_data = PLLVAL(0x4d, 1, 2),  },  /* FVco 680.000000 */
0030     { .frequency = 180000000,   .driver_data = PLLVAL(0x70, 2, 2),  },  /* FVco 720.000000 */
0031     { .frequency = 190000000,   .driver_data = PLLVAL(0x57, 1, 2),  },  /* FVco 760.000000 */
0032     { .frequency = 200000000,   .driver_data = PLLVAL(0x5c, 1, 2),  },  /* FVco 800.000000 */
0033     { .frequency = 210000000,   .driver_data = PLLVAL(0x84, 2, 2),  },  /* FVco 840.000000 */
0034     { .frequency = 220000000,   .driver_data = PLLVAL(0x66, 1, 2),  },  /* FVco 880.000000 */
0035     { .frequency = 230000000,   .driver_data = PLLVAL(0x6b, 1, 2),  },  /* FVco 920.000000 */
0036     { .frequency = 240000000,   .driver_data = PLLVAL(0x70, 1, 2),  },  /* FVco 960.000000 */
0037     { .frequency = 300000000,   .driver_data = PLLVAL(0x75, 3, 1),  },  /* FVco 600.000000 */
0038     { .frequency = 310000000,   .driver_data = PLLVAL(0x93, 4, 1),  },  /* FVco 620.000000 */
0039     { .frequency = 320000000,   .driver_data = PLLVAL(0x98, 4, 1),  },  /* FVco 640.000000 */
0040     { .frequency = 330000000,   .driver_data = PLLVAL(0x66, 2, 1),  },  /* FVco 660.000000 */
0041     { .frequency = 340000000,   .driver_data = PLLVAL(0x4d, 1, 1),  },  /* FVco 680.000000 */
0042     { .frequency = 350000000,   .driver_data = PLLVAL(0xa7, 4, 1),  },  /* FVco 700.000000 */
0043     { .frequency = 360000000,   .driver_data = PLLVAL(0x70, 2, 1),  },  /* FVco 720.000000 */
0044     { .frequency = 370000000,   .driver_data = PLLVAL(0xb1, 4, 1),  },  /* FVco 740.000000 */
0045     { .frequency = 380000000,   .driver_data = PLLVAL(0x57, 1, 1),  },  /* FVco 760.000000 */
0046     { .frequency = 390000000,   .driver_data = PLLVAL(0x7a, 2, 1),  },  /* FVco 780.000000 */
0047     { .frequency = 400000000,   .driver_data = PLLVAL(0x5c, 1, 1),  },  /* FVco 800.000000 */
0048 };
0049
0050 static int s3c2440_plls12_add(struct device *dev, struct subsys_interface *sif)
0051 {
0052     struct clk *xtal_clk;
0053     unsigned long xtal;
0054
0055     xtal_clk = clk_get(NULL, "xtal");
0056     if (IS_ERR(xtal_clk))
0057         return PTR_ERR(xtal_clk);
0058
0059     xtal = clk_get_rate(xtal_clk);
0060     clk_put(xtal_clk);
0061
0062     if (xtal == 12000000) {
0063         printk(KERN_INFO "Using PLL table for 12MHz crystal\n");
0064         return s3c_plltab_register(s3c2440_plls_12,
0065                        ARRAY_SIZE(s3c2440_plls_12));
0066     }
0067
0068     return 0;
0069 }
0070
0071 static struct subsys_interface s3c2440_plls12_interface = {
0072     .name       = "s3c2440_plls12",
0073     .subsys     = &s3c2440_subsys,
0074     .add_dev    = s3c2440_plls12_add,
0075 };
0076
0077 static int __init s3c2440_pll_12mhz(void)
0078 {
0079     return subsys_interface_register(&s3c2440_plls12_interface);
0080
0081 }
0082 arch_initcall(s3c2440_pll_12mhz);
0083
0084 static struct subsys_interface s3c2442_plls12_interface = {
0085     .name       = "s3c2442_plls12",
0086     .subsys     = &s3c2442_subsys,
0087     .add_dev    = s3c2440_plls12_add,
0088 };
0089
0090 static int __init s3c2442_pll_12mhz(void)
0091 {
0092     return subsys_interface_register(&s3c2442_plls12_interface);
0093
0094 }
0095 arch_initcall(s3c2442_pll_12mhz);