arm/mach-s3c/pll-s3c2410.c

0001 // SPDX-License-Identifier: GPL-2.0+
0002 //
0003 // Copyright (c) 2006-2007 Simtec Electronics
0004 //  http://armlinux.simtec.co.uk/
0005 //  Ben Dooks <ben@simtec.co.uk>
0006 //  Vincent Sanders <vince@arm.linux.org.uk>
0007 //
0008 // S3C2410 CPU PLL tables
0009
0010 #include <linux/types.h>
0011 #include <linux/kernel.h>
0012 #include <linux/module.h>
0013 #include <linux/device.h>
0014 #include <linux/list.h>
0015 #include <linux/clk.h>
0016 #include <linux/err.h>
0017
0018 #include <linux/soc/samsung/s3c-cpufreq-core.h>
0019 #include <linux/soc/samsung/s3c-pm.h>
0020
0021 /* This array should be sorted in ascending order of the frequencies */
0022 static struct cpufreq_frequency_table pll_vals_12MHz[] = {
0023     { .frequency = 34000000,  .driver_data = PLLVAL(82, 2, 3),   },
0024     { .frequency = 45000000,  .driver_data = PLLVAL(82, 1, 3),   },
0025     { .frequency = 48000000,  .driver_data = PLLVAL(120, 2, 3),  },
0026     { .frequency = 51000000,  .driver_data = PLLVAL(161, 3, 3),  },
0027     { .frequency = 56000000,  .driver_data = PLLVAL(142, 2, 3),  },
0028     { .frequency = 68000000,  .driver_data = PLLVAL(82, 2, 2),   },
0029     { .frequency = 79000000,  .driver_data = PLLVAL(71, 1, 2),   },
0030     { .frequency = 85000000,  .driver_data = PLLVAL(105, 2, 2),  },
0031     { .frequency = 90000000,  .driver_data = PLLVAL(112, 2, 2),  },
0032     { .frequency = 101000000, .driver_data = PLLVAL(127, 2, 2),  },
0033     { .frequency = 113000000, .driver_data = PLLVAL(105, 1, 2),  },
0034     { .frequency = 118000000, .driver_data = PLLVAL(150, 2, 2),  },
0035     { .frequency = 124000000, .driver_data = PLLVAL(116, 1, 2),  },
0036     { .frequency = 135000000, .driver_data = PLLVAL(82, 2, 1),   },
0037     { .frequency = 147000000, .driver_data = PLLVAL(90, 2, 1),   },
0038     { .frequency = 152000000, .driver_data = PLLVAL(68, 1, 1),   },
0039     { .frequency = 158000000, .driver_data = PLLVAL(71, 1, 1),   },
0040     { .frequency = 170000000, .driver_data = PLLVAL(77, 1, 1),   },
0041     { .frequency = 180000000, .driver_data = PLLVAL(82, 1, 1),   },
0042     { .frequency = 186000000, .driver_data = PLLVAL(85, 1, 1),   },
0043     { .frequency = 192000000, .driver_data = PLLVAL(88, 1, 1),   },
0044     { .frequency = 203000000, .driver_data = PLLVAL(161, 3, 1),  },
0045
0046     /* 2410A extras */
0047
0048     { .frequency = 210000000, .driver_data = PLLVAL(132, 2, 1),  },
0049     { .frequency = 226000000, .driver_data = PLLVAL(105, 1, 1),  },
0050     { .frequency = 266000000, .driver_data = PLLVAL(125, 1, 1),  },
0051     { .frequency = 268000000, .driver_data = PLLVAL(126, 1, 1),  },
0052     { .frequency = 270000000, .driver_data = PLLVAL(127, 1, 1),  },
0053 };
0054
0055 static int s3c2410_plls_add(struct device *dev, struct subsys_interface *sif)
0056 {
0057     return s3c_plltab_register(pll_vals_12MHz, ARRAY_SIZE(pll_vals_12MHz));
0058 }
0059
0060 static struct subsys_interface s3c2410_plls_interface = {
0061     .name       = "s3c2410_plls",
0062     .subsys     = &s3c2410_subsys,
0063     .add_dev    = s3c2410_plls_add,
0064 };
0065
0066 static int __init s3c2410_pll_init(void)
0067 {
0068     return subsys_interface_register(&s3c2410_plls_interface);
0069
0070 }
0071 arch_initcall(s3c2410_pll_init);
0072
0073 static struct subsys_interface s3c2410a_plls_interface = {
0074     .name       = "s3c2410a_plls",
0075     .subsys     = &s3c2410a_subsys,
0076     .add_dev    = s3c2410_plls_add,
0077 };
0078
0079 static int __init s3c2410a_pll_init(void)
0080 {
0081     return subsys_interface_register(&s3c2410a_plls_interface);
0082 }
0083 arch_initcall(s3c2410a_pll_init);