arm/mach-s3c/osiris.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright 2005 Simtec Electronics
0004  *  http://www.simtec.co.uk/products/
0005  *  Ben Dooks <ben@simtec.co.uk>
0006  *
0007  * OSIRIS - CPLD control constants
0008  * OSIRIS - Memory map definitions
0009  */
0010
0011 #ifndef __MACH_S3C24XX_OSIRIS_H
0012 #define __MACH_S3C24XX_OSIRIS_H __FILE__
0013
0014 /* CTRL0 - NAND WP control */
0015
0016 #define OSIRIS_CTRL0_NANDSEL        (0x3)
0017 #define OSIRIS_CTRL0_BOOT_INT       (1<<3)
0018 #define OSIRIS_CTRL0_PCMCIA     (1<<4)
0019 #define OSIRIS_CTRL0_FIX8       (1<<5)
0020 #define OSIRIS_CTRL0_PCMCIA_nWAIT   (1<<6)
0021 #define OSIRIS_CTRL0_PCMCIA_nIOIS16 (1<<7)
0022
0023 #define OSIRIS_CTRL1_FIX8       (1<<0)
0024
0025 #define OSIRIS_ID_REVMASK       (0x7)
0026
0027 /* start peripherals off after the S3C2410 */
0028
0029 #define OSIRIS_IOADDR(x)    (S3C2410_ADDR((x) + 0x04000000))
0030
0031 #define OSIRIS_PA_CPLD      (S3C2410_CS1 | (1<<26))
0032
0033 /* we put the CPLD registers next, to get them out of the way */
0034
0035 #define OSIRIS_VA_CTRL0     OSIRIS_IOADDR(0x00000000)
0036 #define OSIRIS_PA_CTRL0     (OSIRIS_PA_CPLD)
0037
0038 #define OSIRIS_VA_CTRL1     OSIRIS_IOADDR(0x00100000)
0039 #define OSIRIS_PA_CTRL1     (OSIRIS_PA_CPLD + (1<<23))
0040
0041 #define OSIRIS_VA_CTRL2     OSIRIS_IOADDR(0x00200000)
0042 #define OSIRIS_PA_CTRL2     (OSIRIS_PA_CPLD + (2<<23))
0043
0044 #define OSIRIS_VA_CTRL3     OSIRIS_IOADDR(0x00300000)
0045 #define OSIRIS_PA_CTRL3     (OSIRIS_PA_CPLD + (2<<23))
0046
0047 #define OSIRIS_VA_IDREG     OSIRIS_IOADDR(0x00700000)
0048 #define OSIRIS_PA_IDREG     (OSIRIS_PA_CPLD + (7<<23))
0049
0050 #endif /* __MACH_S3C24XX_OSIRIS_H */