arm/mach-s3c/map-s3c24xx.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright (c) 2003 Simtec Electronics
0004  *  Ben Dooks <ben@simtec.co.uk>
0005  *
0006  * S3C2410 - Memory map definitions
0007  */
0008
0009 #ifndef __ASM_ARCH_MAP_H
0010 #define __ASM_ARCH_MAP_H
0011
0012 #include "map-base.h"
0013 #include "map-s3c.h"
0014
0015 /*
0016  * interrupt controller is the first thing we put in, to make
0017  * the assembly code for the irq detection easier
0018  */
0019 #define S3C2410_PA_IRQ      (0x4A000000)
0020 #define S3C24XX_SZ_IRQ      SZ_1M
0021
0022 /* memory controller registers */
0023 #define S3C2410_PA_MEMCTRL  (0x48000000)
0024 #define S3C24XX_SZ_MEMCTRL  SZ_1M
0025
0026 /* Timers */
0027 #define S3C2410_PA_TIMER    (0x51000000)
0028 #define S3C24XX_SZ_TIMER    SZ_1M
0029
0030 /* Clock and Power management */
0031 #define S3C24XX_SZ_CLKPWR   SZ_1M
0032
0033 /* USB Device port */
0034 #define S3C2410_PA_USBDEV   (0x52000000)
0035 #define S3C24XX_SZ_USBDEV   SZ_1M
0036
0037 /* Watchdog */
0038 #define S3C2410_PA_WATCHDOG (0x53000000)
0039 #define S3C24XX_SZ_WATCHDOG SZ_1M
0040
0041 /* Standard size definitions for peripheral blocks. */
0042
0043 #define S3C24XX_SZ_UART     SZ_1M
0044 #define S3C24XX_SZ_IIS      SZ_1M
0045 #define S3C24XX_SZ_ADC      SZ_1M
0046 #define S3C24XX_SZ_SPI      SZ_1M
0047 #define S3C24XX_SZ_SDI      SZ_1M
0048 #define S3C24XX_SZ_NAND     SZ_1M
0049 #define S3C24XX_SZ_GPIO     SZ_1M
0050
0051 /* USB host controller */
0052 #define S3C2410_PA_USBHOST (0x49000000)
0053
0054 /* S3C2416/S3C2443/S3C2450 High-Speed USB Gadget */
0055 #define S3C2416_PA_HSUDC    (0x49800000)
0056 #define S3C2416_SZ_HSUDC    (SZ_4K)
0057
0058 /* DMA controller */
0059 #define S3C2410_PA_DMA     (0x4B000000)
0060 #define S3C24XX_SZ_DMA     SZ_1M
0061
0062 /* Clock and Power management */
0063 #define S3C2410_PA_CLKPWR  (0x4C000000)
0064
0065 /* LCD controller */
0066 #define S3C2410_PA_LCD     (0x4D000000)
0067 #define S3C24XX_SZ_LCD     SZ_1M
0068
0069 /* NAND flash controller */
0070 #define S3C2410_PA_NAND    (0x4E000000)
0071
0072 /* IIC hardware controller */
0073 #define S3C2410_PA_IIC     (0x54000000)
0074
0075 /* IIS controller */
0076 #define S3C2410_PA_IIS     (0x55000000)
0077
0078 /* RTC */
0079 #define S3C2410_PA_RTC     (0x57000000)
0080 #define S3C24XX_SZ_RTC     SZ_1M
0081
0082 /* ADC */
0083 #define S3C2410_PA_ADC     (0x58000000)
0084
0085 /* SPI */
0086 #define S3C2410_PA_SPI     (0x59000000)
0087 #define S3C2443_PA_SPI0     (0x52000000)
0088 #define S3C2443_PA_SPI1     S3C2410_PA_SPI
0089 #define S3C2410_SPI1        (0x20)
0090 #define S3C2412_SPI1        (0x100)
0091
0092 /* SDI */
0093 #define S3C2410_PA_SDI     (0x5A000000)
0094
0095 /* CAMIF */
0096 #define S3C2440_PA_CAMIF   (0x4F000000)
0097 #define S3C2440_SZ_CAMIF   SZ_1M
0098
0099 /* AC97 */
0100
0101 #define S3C2440_PA_AC97    (0x5B000000)
0102 #define S3C2440_SZ_AC97    SZ_1M
0103
0104 /* S3C2443/S3C2416 High-speed SD/MMC */
0105 #define S3C2443_PA_HSMMC   (0x4A800000)
0106 #define S3C2416_PA_HSMMC0  (0x4AC00000)
0107
0108 #define S3C2443_PA_FB   (0x4C800000)
0109
0110 /* S3C2412 memory and IO controls */
0111 #define S3C2412_PA_SSMC (0x4F000000)
0112
0113 #define S3C2412_PA_EBI  (0x48800000)
0114
0115 /* physical addresses of all the chip-select areas */
0116
0117 #define S3C2410_CS0 (0x00000000)
0118 #define S3C2410_CS1 (0x08000000)
0119 #define S3C2410_CS2 (0x10000000)
0120 #define S3C2410_CS3 (0x18000000)
0121 #define S3C2410_CS4 (0x20000000)
0122 #define S3C2410_CS5 (0x28000000)
0123 #define S3C2410_CS6 (0x30000000)
0124 #define S3C2410_CS7 (0x38000000)
0125
0126 #define S3C2410_SDRAM_PA    (S3C2410_CS6)
0127
0128 /* Use a single interface for common resources between S3C24XX cpus */
0129
0130 #define S3C24XX_PA_IRQ      S3C2410_PA_IRQ
0131 #define S3C24XX_PA_MEMCTRL  S3C2410_PA_MEMCTRL
0132 #define S3C24XX_PA_DMA      S3C2410_PA_DMA
0133 #define S3C24XX_PA_CLKPWR   S3C2410_PA_CLKPWR
0134 #define S3C24XX_PA_LCD      S3C2410_PA_LCD
0135 #define S3C24XX_PA_TIMER    S3C2410_PA_TIMER
0136 #define S3C24XX_PA_USBDEV   S3C2410_PA_USBDEV
0137 #define S3C24XX_PA_WATCHDOG S3C2410_PA_WATCHDOG
0138 #define S3C24XX_PA_IIS      S3C2410_PA_IIS
0139 #define S3C24XX_PA_RTC      S3C2410_PA_RTC
0140 #define S3C24XX_PA_ADC      S3C2410_PA_ADC
0141 #define S3C24XX_PA_SPI      S3C2410_PA_SPI
0142 #define S3C24XX_PA_SPI1     (S3C2410_PA_SPI + S3C2410_SPI1)
0143 #define S3C24XX_PA_SDI      S3C2410_PA_SDI
0144 #define S3C24XX_PA_NAND     S3C2410_PA_NAND
0145
0146 #define S3C_PA_FB       S3C2443_PA_FB
0147 #define S3C_PA_IIC          S3C2410_PA_IIC
0148 #define S3C_PA_USBHOST  S3C2410_PA_USBHOST
0149 #define S3C_PA_HSMMC0       S3C2416_PA_HSMMC0
0150 #define S3C_PA_HSMMC1       S3C2443_PA_HSMMC
0151 #define S3C_PA_WDT      S3C2410_PA_WATCHDOG
0152 #define S3C_PA_NAND     S3C24XX_PA_NAND
0153
0154 #define S3C_PA_SPI0     S3C2443_PA_SPI0
0155 #define S3C_PA_SPI1     S3C2443_PA_SPI1
0156
0157 #define SAMSUNG_PA_TIMER    S3C2410_PA_TIMER
0158
0159 #endif /* __ASM_ARCH_MAP_H */