arm/mach-s3c/mach-rx3715.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 //
0003 // Copyright (c) 2003-2004 Simtec Electronics
0004 //  Ben Dooks <ben@simtec.co.uk>
0005 //
0006 // https://www.handhelds.org/projects/rx3715.html
0007
0008 #include <linux/kernel.h>
0009 #include <linux/types.h>
0010 #include <linux/interrupt.h>
0011 #include <linux/list.h>
0012 #include <linux/memblock.h>
0013 #include <linux/timer.h>
0014 #include <linux/init.h>
0015 #include <linux/tty.h>
0016 #include <linux/console.h>
0017 #include <linux/device.h>
0018 #include <linux/platform_device.h>
0019 #include <linux/serial_core.h>
0020 #include <linux/serial_s3c.h>
0021 #include <linux/serial.h>
0022 #include <linux/io.h>
0023 #include <linux/mtd/mtd.h>
0024 #include <linux/mtd/rawnand.h>
0025 #include <linux/mtd/nand-ecc-sw-hamming.h>
0026 #include <linux/mtd/partitions.h>
0027
0028 #include <asm/mach/arch.h>
0029 #include <asm/mach/irq.h>
0030 #include <asm/mach/map.h>
0031
0032 #include <linux/platform_data/mtd-nand-s3c2410.h>
0033 #include <linux/platform_data/fb-s3c2410.h>
0034
0035 #include <asm/irq.h>
0036 #include <asm/mach-types.h>
0037
0038 #include "regs-gpio.h"
0039 #include "gpio-samsung.h"
0040 #include "gpio-cfg.h"
0041
0042 #include "cpu.h"
0043 #include "devs.h"
0044 #include "pm.h"
0045
0046 #include "s3c24xx.h"
0047 #include "h1940.h"
0048
0049 static struct map_desc rx3715_iodesc[] __initdata = {
0050     /* dump ISA space somewhere unused */
0051     {
0052         .virtual    = (u32)S3C24XX_VA_ISA_BYTE,
0053         .pfn        = __phys_to_pfn(S3C2410_CS3),
0054         .length     = SZ_1M,
0055         .type       = MT_DEVICE,
0056     },
0057 };
0058
0059 static struct s3c2410_uartcfg rx3715_uartcfgs[] = {
0060     [0] = {
0061         .hwport      = 0,
0062         .flags       = 0,
0063         .ucon        = 0x3c5,
0064         .ulcon       = 0x03,
0065         .ufcon       = 0x51,
0066         .clk_sel    = S3C2410_UCON_CLKSEL3,
0067     },
0068     [1] = {
0069         .hwport      = 1,
0070         .flags       = 0,
0071         .ucon        = 0x3c5,
0072         .ulcon       = 0x03,
0073         .ufcon       = 0x00,
0074         .clk_sel    = S3C2410_UCON_CLKSEL3,
0075     },
0076     /* IR port */
0077     [2] = {
0078         .hwport      = 2,
0079         .uart_flags  = UPF_CONS_FLOW,
0080         .ucon        = 0x3c5,
0081         .ulcon       = 0x43,
0082         .ufcon       = 0x51,
0083         .clk_sel    = S3C2410_UCON_CLKSEL3,
0084     }
0085 };
0086
0087 /* framebuffer lcd controller information */
0088
0089 static struct s3c2410fb_display rx3715_lcdcfg __initdata = {
0090     .lcdcon5 =  S3C2410_LCDCON5_INVVLINE |
0091             S3C2410_LCDCON5_FRM565 |
0092             S3C2410_LCDCON5_HWSWP,
0093
0094     .type       = S3C2410_LCDCON1_TFT,
0095     .width      = 240,
0096     .height     = 320,
0097
0098     .pixclock   = 260000,
0099     .xres       = 240,
0100     .yres       = 320,
0101     .bpp        = 16,
0102     .left_margin    = 36,
0103     .right_margin   = 36,
0104     .hsync_len  = 8,
0105     .upper_margin   = 6,
0106     .lower_margin   = 7,
0107     .vsync_len  = 3,
0108 };
0109
0110 static struct s3c2410fb_mach_info rx3715_fb_info __initdata = {
0111
0112     .displays = &rx3715_lcdcfg,
0113     .num_displays = 1,
0114     .default_display = 0,
0115
0116     .lpcsel =   0xf82,
0117
0118     .gpccon =   0xaa955699,
0119     .gpccon_mask =  0xffc003cc,
0120     .gpccon_reg =   S3C2410_GPCCON,
0121     .gpcup =    0x0000ffff,
0122     .gpcup_mask =   0xffffffff,
0123     .gpcup_reg =    S3C2410_GPCUP,
0124
0125     .gpdcon =   0xaa95aaa1,
0126     .gpdcon_mask =  0xffc0fff0,
0127     .gpdcon_reg =   S3C2410_GPDCON,
0128     .gpdup =    0x0000faff,
0129     .gpdup_mask =   0xffffffff,
0130     .gpdup_reg =    S3C2410_GPDUP,
0131 };
0132
0133 static struct mtd_partition __initdata rx3715_nand_part[] = {
0134     [0] = {
0135         .name       = "Whole Flash",
0136         .offset     = 0,
0137         .size       = MTDPART_SIZ_FULL,
0138         .mask_flags = MTD_WRITEABLE,
0139     }
0140 };
0141
0142 static struct s3c2410_nand_set __initdata rx3715_nand_sets[] = {
0143     [0] = {
0144         .name       = "Internal",
0145         .nr_chips   = 1,
0146         .nr_partitions  = ARRAY_SIZE(rx3715_nand_part),
0147         .partitions = rx3715_nand_part,
0148     },
0149 };
0150
0151 static struct s3c2410_platform_nand __initdata rx3715_nand_info = {
0152     .tacls      = 25,
0153     .twrph0     = 50,
0154     .twrph1     = 15,
0155     .nr_sets    = ARRAY_SIZE(rx3715_nand_sets),
0156     .sets       = rx3715_nand_sets,
0157     .engine_type    = NAND_ECC_ENGINE_TYPE_SOFT,
0158 };
0159
0160 static struct platform_device *rx3715_devices[] __initdata = {
0161     &s3c_device_ohci,
0162     &s3c_device_lcd,
0163     &s3c_device_wdt,
0164     &s3c_device_i2c0,
0165     &s3c_device_iis,
0166     &s3c_device_nand,
0167 };
0168
0169 static void __init rx3715_map_io(void)
0170 {
0171     s3c24xx_init_io(rx3715_iodesc, ARRAY_SIZE(rx3715_iodesc));
0172     s3c24xx_init_uarts(rx3715_uartcfgs, ARRAY_SIZE(rx3715_uartcfgs));
0173     s3c24xx_set_timer_source(S3C24XX_PWM3, S3C24XX_PWM4);
0174 }
0175
0176 static void __init rx3715_init_time(void)
0177 {
0178     s3c2440_init_clocks(16934000);
0179     s3c24xx_timer_init();
0180 }
0181
0182 /* H1940 and RX3715 need to reserve this for suspend */
0183 static void __init rx3715_reserve(void)
0184 {
0185     memblock_reserve(0x30003000, 0x1000);
0186     memblock_reserve(0x30081000, 0x1000);
0187 }
0188
0189 static void __init rx3715_init_machine(void)
0190 {
0191 #ifdef CONFIG_PM_H1940
0192     memcpy(phys_to_virt(H1940_SUSPEND_RESUMEAT), h1940_pm_return, 1024);
0193 #endif
0194     s3c_pm_init();
0195
0196     s3c_nand_set_platdata(&rx3715_nand_info);
0197     s3c24xx_fb_set_platdata(&rx3715_fb_info);
0198     /* Configure the I2S pins (GPE0...GPE4) in correct mode */
0199     s3c_gpio_cfgall_range(S3C2410_GPE(0), 5, S3C_GPIO_SFN(2),
0200                   S3C_GPIO_PULL_NONE);
0201     platform_add_devices(rx3715_devices, ARRAY_SIZE(rx3715_devices));
0202 }
0203
0204 MACHINE_START(RX3715, "IPAQ-RX3715")
0205     /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
0206     .atag_offset    = 0x100,
0207     .nr_irqs    = NR_IRQS_S3C2440,
0208     .map_io     = rx3715_map_io,
0209     .reserve    = rx3715_reserve,
0210     .init_irq   = s3c2440_init_irq,
0211     .init_machine   = rx3715_init_machine,
0212     .init_time  = rx3715_init_time,
0213 MACHINE_END