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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0
0002 //
0003 // Copyright 2007 Simtec Electronics
0004 //  Ben Dooks <ben@simtec.co.uk>
0005 //
0006 // http://armlinux.simtec.co.uk/
0007 
0008 #include <linux/kernel.h>
0009 #include <linux/types.h>
0010 #include <linux/interrupt.h>
0011 #include <linux/list.h>
0012 #include <linux/timer.h>
0013 #include <linux/init.h>
0014 #include <linux/gpio.h>
0015 #include <linux/gpio/machine.h>
0016 #include <linux/syscore_ops.h>
0017 #include <linux/serial_core.h>
0018 #include <linux/serial_s3c.h>
0019 #include <linux/platform_device.h>
0020 #include <linux/i2c.h>
0021 
0022 #include <video/ili9320.h>
0023 
0024 #include <linux/spi/spi.h>
0025 #include <linux/spi/spi_gpio.h>
0026 
0027 #include <asm/mach/arch.h>
0028 #include <asm/mach/map.h>
0029 #include <asm/mach/irq.h>
0030 
0031 #include <linux/platform_data/mtd-nand-s3c2410.h>
0032 #include <linux/platform_data/i2c-s3c2410.h>
0033 
0034 #include "hardware-s3c24xx.h"
0035 #include "regs-gpio.h"
0036 #include <linux/platform_data/fb-s3c2410.h>
0037 #include "gpio-samsung.h"
0038 
0039 #include <asm/mach-types.h>
0040 
0041 #include <linux/mtd/mtd.h>
0042 #include <linux/mtd/rawnand.h>
0043 #include <linux/mtd/nand-ecc-sw-hamming.h>
0044 #include <linux/mtd/partitions.h>
0045 
0046 #include "gpio-cfg.h"
0047 #include "devs.h"
0048 #include "cpu.h"
0049 #include "pm.h"
0050 #include <linux/platform_data/usb-s3c2410_udc.h>
0051 
0052 #include "s3c24xx.h"
0053 #include "s3c2412-power.h"
0054 
0055 static struct map_desc jive_iodesc[] __initdata = {
0056 };
0057 
0058 #define UCON S3C2410_UCON_DEFAULT
0059 #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE
0060 #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
0061 
0062 static struct s3c2410_uartcfg jive_uartcfgs[] = {
0063     [0] = {
0064         .hwport      = 0,
0065         .flags       = 0,
0066         .ucon        = UCON,
0067         .ulcon       = ULCON,
0068         .ufcon       = UFCON,
0069     },
0070     [1] = {
0071         .hwport      = 1,
0072         .flags       = 0,
0073         .ucon        = UCON,
0074         .ulcon       = ULCON,
0075         .ufcon       = UFCON,
0076     },
0077     [2] = {
0078         .hwport      = 2,
0079         .flags       = 0,
0080         .ucon        = UCON,
0081         .ulcon       = ULCON,
0082         .ufcon       = UFCON,
0083     }
0084 };
0085 
0086 /* Jive flash assignment
0087  *
0088  * 0x00000000-0x00028000 : uboot
0089  * 0x00028000-0x0002c000 : uboot env
0090  * 0x0002c000-0x00030000 : spare
0091  * 0x00030000-0x00200000 : zimage A
0092  * 0x00200000-0x01600000 : cramfs A
0093  * 0x01600000-0x017d0000 : zimage B
0094  * 0x017d0000-0x02bd0000 : cramfs B
0095  * 0x02bd0000-0x03fd0000 : yaffs
0096  */
0097 static struct mtd_partition __initdata jive_imageA_nand_part[] = {
0098 
0099 #ifdef CONFIG_MACH_JIVE_SHOW_BOOTLOADER
0100     /* Don't allow access to the bootloader from linux */
0101     {
0102         .name           = "uboot",
0103         .offset         = 0,
0104         .size           = (160 * SZ_1K),
0105         .mask_flags = MTD_WRITEABLE, /* force read-only */
0106     },
0107 
0108     /* spare */
0109         {
0110                 .name           = "spare",
0111                 .offset         = (176 * SZ_1K),
0112                 .size           = (16 * SZ_1K),
0113         },
0114 #endif
0115 
0116     /* booted images */
0117         {
0118         .name       = "kernel (ro)",
0119         .offset     = (192 * SZ_1K),
0120         .size       = (SZ_2M) - (192 * SZ_1K),
0121         .mask_flags = MTD_WRITEABLE, /* force read-only */
0122         }, {
0123                 .name           = "root (ro)",
0124                 .offset         = (SZ_2M),
0125                 .size           = (20 * SZ_1M),
0126         .mask_flags = MTD_WRITEABLE, /* force read-only */
0127         },
0128 
0129     /* yaffs */
0130     {
0131         .name       = "yaffs",
0132         .offset     = (44 * SZ_1M),
0133         .size       = (20 * SZ_1M),
0134     },
0135 
0136     /* bootloader environment */
0137     {
0138                 .name       = "env",
0139         .offset     = (160 * SZ_1K),
0140         .size       = (16 * SZ_1K),
0141     },
0142 
0143     /* upgrade images */
0144         {
0145         .name       = "zimage",
0146         .offset     = (22 * SZ_1M),
0147         .size       = (2 * SZ_1M) - (192 * SZ_1K),
0148         }, {
0149         .name       = "cramfs",
0150         .offset     = (24 * SZ_1M) - (192*SZ_1K),
0151         .size       = (20 * SZ_1M),
0152         },
0153 };
0154 
0155 static struct mtd_partition __initdata jive_imageB_nand_part[] = {
0156 
0157 #ifdef CONFIG_MACH_JIVE_SHOW_BOOTLOADER
0158     /* Don't allow access to the bootloader from linux */
0159     {
0160         .name           = "uboot",
0161         .offset         = 0,
0162         .size           = (160 * SZ_1K),
0163         .mask_flags = MTD_WRITEABLE, /* force read-only */
0164     },
0165 
0166     /* spare */
0167         {
0168                 .name           = "spare",
0169                 .offset         = (176 * SZ_1K),
0170                 .size           = (16 * SZ_1K),
0171         },
0172 #endif
0173 
0174     /* booted images */
0175         {
0176         .name           = "kernel (ro)",
0177         .offset         = (22 * SZ_1M),
0178         .size           = (2 * SZ_1M) - (192 * SZ_1K),
0179         .mask_flags = MTD_WRITEABLE, /* force read-only */
0180         },
0181     {
0182         .name       = "root (ro)",
0183         .offset     = (24 * SZ_1M) - (192 * SZ_1K),
0184                 .size       = (20 * SZ_1M),
0185         .mask_flags = MTD_WRITEABLE, /* force read-only */
0186     },
0187 
0188     /* yaffs */
0189     {
0190         .name       = "yaffs",
0191         .offset     = (44 * SZ_1M),
0192         .size       = (20 * SZ_1M),
0193         },
0194 
0195     /* bootloader environment */
0196     {
0197         .name       = "env",
0198         .offset     = (160 * SZ_1K),
0199         .size       = (16 * SZ_1K),
0200     },
0201 
0202     /* upgrade images */
0203     {
0204         .name       = "zimage",
0205         .offset     = (192 * SZ_1K),
0206         .size       = (2 * SZ_1M) - (192 * SZ_1K),
0207         }, {
0208         .name       = "cramfs",
0209         .offset     = (2 * SZ_1M),
0210         .size       = (20 * SZ_1M),
0211         },
0212 };
0213 
0214 static struct s3c2410_nand_set __initdata jive_nand_sets[] = {
0215     [0] = {
0216         .name           = "flash",
0217         .nr_chips       = 1,
0218         .nr_partitions  = ARRAY_SIZE(jive_imageA_nand_part),
0219         .partitions     = jive_imageA_nand_part,
0220     },
0221 };
0222 
0223 static struct s3c2410_platform_nand __initdata jive_nand_info = {
0224     /* set taken from osiris nand timings, possibly still conservative */
0225     .tacls      = 30,
0226     .twrph0     = 55,
0227     .twrph1     = 40,
0228     .sets       = jive_nand_sets,
0229     .nr_sets    = ARRAY_SIZE(jive_nand_sets),
0230     .engine_type    = NAND_ECC_ENGINE_TYPE_SOFT,
0231 };
0232 
0233 static int __init jive_mtdset(char *options)
0234 {
0235     struct s3c2410_nand_set *nand = &jive_nand_sets[0];
0236     unsigned long set;
0237 
0238     if (options == NULL || options[0] == '\0')
0239         return 1;
0240 
0241     if (kstrtoul(options, 10, &set)) {
0242         printk(KERN_ERR "failed to parse mtdset=%s\n", options);
0243         return 1;
0244     }
0245 
0246     switch (set) {
0247     case 1:
0248         nand->nr_partitions = ARRAY_SIZE(jive_imageB_nand_part);
0249         nand->partitions = jive_imageB_nand_part;
0250         break;
0251     case 0:
0252         /* this is already setup in the nand info */
0253         break;
0254     default:
0255         printk(KERN_ERR "Unknown mtd set %ld specified,"
0256                "using default.", set);
0257     }
0258 
0259     return 1;
0260 }
0261 
0262 /* parse the mtdset= option given to the kernel command line */
0263 __setup("mtdset=", jive_mtdset);
0264 
0265 /* LCD timing and setup */
0266 
0267 #define LCD_XRES     (240)
0268 #define LCD_YRES     (320)
0269 #define LCD_LEFT_MARGIN  (12)
0270 #define LCD_RIGHT_MARGIN (12)
0271 #define LCD_LOWER_MARGIN (12)
0272 #define LCD_UPPER_MARGIN (12)
0273 #define LCD_VSYNC    (2)
0274 #define LCD_HSYNC    (2)
0275 
0276 #define LCD_REFRESH  (60)
0277 
0278 #define LCD_HTOT (LCD_HSYNC + LCD_LEFT_MARGIN + LCD_XRES + LCD_RIGHT_MARGIN)
0279 #define LCD_VTOT (LCD_VSYNC + LCD_LOWER_MARGIN + LCD_YRES + LCD_UPPER_MARGIN)
0280 
0281 static struct s3c2410fb_display jive_vgg2432a4_display[] = {
0282     [0] = {
0283         .width      = LCD_XRES,
0284         .height     = LCD_YRES,
0285         .xres       = LCD_XRES,
0286         .yres       = LCD_YRES,
0287         .left_margin    = LCD_LEFT_MARGIN,
0288         .right_margin   = LCD_RIGHT_MARGIN,
0289         .upper_margin   = LCD_UPPER_MARGIN,
0290         .lower_margin   = LCD_LOWER_MARGIN,
0291         .hsync_len  = LCD_HSYNC,
0292         .vsync_len  = LCD_VSYNC,
0293 
0294         .pixclock   = (1000000000000LL /
0295                    (LCD_REFRESH * LCD_HTOT * LCD_VTOT)),
0296 
0297         .bpp        = 16,
0298         .type       = (S3C2410_LCDCON1_TFT16BPP |
0299                    S3C2410_LCDCON1_TFT),
0300 
0301         .lcdcon5    = (S3C2410_LCDCON5_FRM565 |
0302                    S3C2410_LCDCON5_INVVLINE |
0303                    S3C2410_LCDCON5_INVVFRAME |
0304                    S3C2410_LCDCON5_INVVDEN |
0305                    S3C2410_LCDCON5_PWREN),
0306     },
0307 };
0308 
0309 /* todo - put into gpio header */
0310 
0311 #define S3C2410_GPCCON_MASK(x)  (3 << ((x) * 2))
0312 #define S3C2410_GPDCON_MASK(x)  (3 << ((x) * 2))
0313 
0314 static struct s3c2410fb_mach_info jive_lcd_config = {
0315     .displays    = jive_vgg2432a4_display,
0316     .num_displays    = ARRAY_SIZE(jive_vgg2432a4_display),
0317     .default_display = 0,
0318 
0319     /* Enable VD[2..7], VD[10..15], VD[18..23] and VCLK, syncs, VDEN
0320      * and disable the pull down resistors on pins we are using for LCD
0321      * data. */
0322 
0323     .gpcup      = (0xf << 1) | (0x3f << 10),
0324     .gpcup_reg  = S3C2410_GPCUP,
0325 
0326     .gpccon     = (S3C2410_GPC1_VCLK   | S3C2410_GPC2_VLINE |
0327                S3C2410_GPC3_VFRAME | S3C2410_GPC4_VM |
0328                S3C2410_GPC10_VD2   | S3C2410_GPC11_VD3 |
0329                S3C2410_GPC12_VD4   | S3C2410_GPC13_VD5 |
0330                S3C2410_GPC14_VD6   | S3C2410_GPC15_VD7),
0331 
0332     .gpccon_mask    = (S3C2410_GPCCON_MASK(1)  | S3C2410_GPCCON_MASK(2)  |
0333                S3C2410_GPCCON_MASK(3)  | S3C2410_GPCCON_MASK(4)  |
0334                S3C2410_GPCCON_MASK(10) | S3C2410_GPCCON_MASK(11) |
0335                S3C2410_GPCCON_MASK(12) | S3C2410_GPCCON_MASK(13) |
0336                S3C2410_GPCCON_MASK(14) | S3C2410_GPCCON_MASK(15)),
0337 
0338     .gpccon_reg = S3C2410_GPCCON,
0339 
0340     .gpdup      = (0x3f << 2) | (0x3f << 10),
0341 
0342     .gpdup_reg  = S3C2410_GPDUP,
0343 
0344     .gpdcon     = (S3C2410_GPD2_VD10  | S3C2410_GPD3_VD11 |
0345                S3C2410_GPD4_VD12  | S3C2410_GPD5_VD13 |
0346                S3C2410_GPD6_VD14  | S3C2410_GPD7_VD15 |
0347                S3C2410_GPD10_VD18 | S3C2410_GPD11_VD19 |
0348                S3C2410_GPD12_VD20 | S3C2410_GPD13_VD21 |
0349                S3C2410_GPD14_VD22 | S3C2410_GPD15_VD23),
0350 
0351     .gpdcon_mask    = (S3C2410_GPDCON_MASK(2)  | S3C2410_GPDCON_MASK(3) |
0352                S3C2410_GPDCON_MASK(4)  | S3C2410_GPDCON_MASK(5) |
0353                S3C2410_GPDCON_MASK(6)  | S3C2410_GPDCON_MASK(7) |
0354                S3C2410_GPDCON_MASK(10) | S3C2410_GPDCON_MASK(11)|
0355                S3C2410_GPDCON_MASK(12) | S3C2410_GPDCON_MASK(13)|
0356                S3C2410_GPDCON_MASK(14) | S3C2410_GPDCON_MASK(15)),
0357 
0358     .gpdcon_reg = S3C2410_GPDCON,
0359 };
0360 
0361 /* ILI9320 support. */
0362 
0363 static void jive_lcm_reset(unsigned int set)
0364 {
0365     printk(KERN_DEBUG "%s(%d)\n", __func__, set);
0366 
0367     gpio_set_value(S3C2410_GPG(13), set);
0368 }
0369 
0370 #undef LCD_UPPER_MARGIN
0371 #define LCD_UPPER_MARGIN 2
0372 
0373 static struct ili9320_platdata jive_lcm_config = {
0374     .hsize      = LCD_XRES,
0375     .vsize      = LCD_YRES,
0376 
0377     .reset      = jive_lcm_reset,
0378     .suspend    = ILI9320_SUSPEND_DEEP,
0379 
0380     .entry_mode = ILI9320_ENTRYMODE_ID(3) | ILI9320_ENTRYMODE_BGR,
0381     .display2   = (ILI9320_DISPLAY2_FP(LCD_UPPER_MARGIN) |
0382                ILI9320_DISPLAY2_BP(LCD_LOWER_MARGIN)),
0383     .display3   = 0x0,
0384     .display4   = 0x0,
0385     .rgb_if1    = (ILI9320_RGBIF1_RIM_RGB18 |
0386                ILI9320_RGBIF1_RM | ILI9320_RGBIF1_CLK_RGBIF),
0387     .rgb_if2    = ILI9320_RGBIF2_DPL,
0388     .interface2 = 0x0,
0389     .interface3 = 0x3,
0390     .interface4 = (ILI9320_INTERFACE4_RTNE(16) |
0391                ILI9320_INTERFACE4_DIVE(1)),
0392     .interface5 = 0x0,
0393     .interface6 = 0x0,
0394 };
0395 
0396 /* LCD SPI support */
0397 
0398 static struct spi_gpio_platform_data jive_lcd_spi = {
0399     .num_chipselect = 1,
0400 };
0401 
0402 static struct platform_device jive_device_lcdspi = {
0403     .name       = "spi_gpio",
0404     .id     = 1,
0405     .dev.platform_data = &jive_lcd_spi,
0406 };
0407 
0408 static struct gpiod_lookup_table jive_lcdspi_gpiod_table = {
0409     .dev_id         = "spi_gpio",
0410     .table          = {
0411         GPIO_LOOKUP("GPIOG", 8,
0412                 "sck", GPIO_ACTIVE_HIGH),
0413         GPIO_LOOKUP("GPIOB", 8,
0414                 "mosi", GPIO_ACTIVE_HIGH),
0415         GPIO_LOOKUP("GPIOB", 7,
0416                 "cs", GPIO_ACTIVE_HIGH),
0417         { },
0418     },
0419 };
0420 
0421 /* WM8750 audio code SPI definition */
0422 
0423 static struct spi_gpio_platform_data jive_wm8750_spi = {
0424     .num_chipselect = 1,
0425 };
0426 
0427 static struct platform_device jive_device_wm8750 = {
0428     .name       = "spi_gpio",
0429     .id     = 2,
0430     .dev.platform_data = &jive_wm8750_spi,
0431 };
0432 
0433 static struct gpiod_lookup_table jive_wm8750_gpiod_table = {
0434     .dev_id         = "spi_gpio",
0435     .table          = {
0436         GPIO_LOOKUP("GPIOB", 4,
0437                 "sck", GPIO_ACTIVE_HIGH),
0438         GPIO_LOOKUP("GPIOB", 9,
0439                 "mosi", GPIO_ACTIVE_HIGH),
0440         GPIO_LOOKUP("GPIOH", 10,
0441                 "cs", GPIO_ACTIVE_HIGH),
0442         { },
0443     },
0444 };
0445 
0446 /* JIVE SPI devices. */
0447 
0448 static struct spi_board_info __initdata jive_spi_devs[] = {
0449     [0] = {
0450         .modalias   = "VGG2432A4",
0451         .bus_num    = 1,
0452         .chip_select    = 0,
0453         .mode       = SPI_MODE_3,   /* CPOL=1, CPHA=1 */
0454         .max_speed_hz   = 100000,
0455         .platform_data  = &jive_lcm_config,
0456     }, {
0457         .modalias   = "WM8750",
0458         .bus_num    = 2,
0459         .chip_select    = 0,
0460         .mode       = SPI_MODE_0,   /* CPOL=0, CPHA=0 */
0461         .max_speed_hz   = 100000,
0462     },
0463 };
0464 
0465 /* I2C bus and device configuration. */
0466 
0467 static struct s3c2410_platform_i2c jive_i2c_cfg __initdata = {
0468     .frequency  = 80 * 1000,
0469     .flags      = S3C_IICFLG_FILTER,
0470     .sda_delay  = 2,
0471 };
0472 
0473 static struct i2c_board_info jive_i2c_devs[] __initdata = {
0474     [0] = {
0475         I2C_BOARD_INFO("lis302dl", 0x1c),
0476         .irq    = IRQ_EINT14,
0477     },
0478 };
0479 
0480 /* The platform devices being used. */
0481 
0482 static struct platform_device *jive_devices[] __initdata = {
0483     &s3c_device_ohci,
0484     &s3c_device_rtc,
0485     &s3c_device_wdt,
0486     &s3c_device_i2c0,
0487     &s3c_device_lcd,
0488     &jive_device_lcdspi,
0489     &jive_device_wm8750,
0490     &s3c_device_nand,
0491     &s3c_device_usbgadget,
0492     &s3c2412_device_dma,
0493 };
0494 
0495 static struct s3c2410_udc_mach_info jive_udc_cfg __initdata = {
0496     .vbus_pin   = S3C2410_GPG(1),       /* detect is on GPG1 */
0497 };
0498 
0499 /* Jive power management device */
0500 
0501 #ifdef CONFIG_PM
0502 static int jive_pm_suspend(void)
0503 {
0504     /* Write the magic value u-boot uses to check for resume into
0505      * the INFORM0 register, and ensure INFORM1 is set to the
0506      * correct address to resume from. */
0507 
0508     __raw_writel(0x2BED, S3C2412_INFORM0);
0509     __raw_writel(__pa_symbol(s3c_cpu_resume), S3C2412_INFORM1);
0510 
0511     return 0;
0512 }
0513 
0514 static void jive_pm_resume(void)
0515 {
0516     __raw_writel(0x0, S3C2412_INFORM0);
0517 }
0518 
0519 #else
0520 #define jive_pm_suspend NULL
0521 #define jive_pm_resume NULL
0522 #endif
0523 
0524 static struct syscore_ops jive_pm_syscore_ops = {
0525     .suspend    = jive_pm_suspend,
0526     .resume     = jive_pm_resume,
0527 };
0528 
0529 static void __init jive_map_io(void)
0530 {
0531     s3c24xx_init_io(jive_iodesc, ARRAY_SIZE(jive_iodesc));
0532     s3c24xx_init_uarts(jive_uartcfgs, ARRAY_SIZE(jive_uartcfgs));
0533     s3c24xx_set_timer_source(S3C24XX_PWM3, S3C24XX_PWM4);
0534 }
0535 
0536 static void __init jive_init_time(void)
0537 {
0538     s3c2412_init_clocks(12000000);
0539     s3c24xx_timer_init();
0540 }
0541 
0542 static void jive_power_off(void)
0543 {
0544     printk(KERN_INFO "powering system down...\n");
0545 
0546     gpio_request_one(S3C2410_GPC(5), GPIOF_OUT_INIT_HIGH, NULL);
0547     gpio_free(S3C2410_GPC(5));
0548 }
0549 
0550 static void __init jive_machine_init(void)
0551 {
0552     /* register system core operations for managing low level suspend */
0553 
0554     register_syscore_ops(&jive_pm_syscore_ops);
0555 
0556     /* write our sleep configurations for the IO. Pull down all unused
0557      * IO, ensure that we have turned off all peripherals we do not
0558      * need, and configure the ones we do need. */
0559 
0560     /* Port B sleep */
0561 
0562     __raw_writel(S3C2412_SLPCON_IN(0)   |
0563              S3C2412_SLPCON_PULL(1) |
0564              S3C2412_SLPCON_HIGH(2) |
0565              S3C2412_SLPCON_PULL(3) |
0566              S3C2412_SLPCON_PULL(4) |
0567              S3C2412_SLPCON_PULL(5) |
0568              S3C2412_SLPCON_PULL(6) |
0569              S3C2412_SLPCON_HIGH(7) |
0570              S3C2412_SLPCON_PULL(8) |
0571              S3C2412_SLPCON_PULL(9) |
0572              S3C2412_SLPCON_PULL(10), S3C2412_GPBSLPCON);
0573 
0574     /* Port C sleep */
0575 
0576     __raw_writel(S3C2412_SLPCON_PULL(0) |
0577              S3C2412_SLPCON_PULL(1) |
0578              S3C2412_SLPCON_PULL(2) |
0579              S3C2412_SLPCON_PULL(3) |
0580              S3C2412_SLPCON_PULL(4) |
0581              S3C2412_SLPCON_PULL(5) |
0582              S3C2412_SLPCON_LOW(6)  |
0583              S3C2412_SLPCON_PULL(6) |
0584              S3C2412_SLPCON_PULL(7) |
0585              S3C2412_SLPCON_PULL(8) |
0586              S3C2412_SLPCON_PULL(9) |
0587              S3C2412_SLPCON_PULL(10) |
0588              S3C2412_SLPCON_PULL(11) |
0589              S3C2412_SLPCON_PULL(12) |
0590              S3C2412_SLPCON_PULL(13) |
0591              S3C2412_SLPCON_PULL(14) |
0592              S3C2412_SLPCON_PULL(15), S3C2412_GPCSLPCON);
0593 
0594     /* Port D sleep */
0595 
0596     __raw_writel(S3C2412_SLPCON_ALL_PULL, S3C2412_GPDSLPCON);
0597 
0598     /* Port F sleep */
0599 
0600     __raw_writel(S3C2412_SLPCON_LOW(0)  |
0601              S3C2412_SLPCON_LOW(1)  |
0602              S3C2412_SLPCON_LOW(2)  |
0603              S3C2412_SLPCON_EINT(3) |
0604              S3C2412_SLPCON_EINT(4) |
0605              S3C2412_SLPCON_EINT(5) |
0606              S3C2412_SLPCON_EINT(6) |
0607              S3C2412_SLPCON_EINT(7), S3C2412_GPFSLPCON);
0608 
0609     /* Port G sleep */
0610 
0611     __raw_writel(S3C2412_SLPCON_IN(0)    |
0612              S3C2412_SLPCON_IN(1)    |
0613              S3C2412_SLPCON_IN(2)    |
0614              S3C2412_SLPCON_IN(3)    |
0615              S3C2412_SLPCON_IN(4)    |
0616              S3C2412_SLPCON_IN(5)    |
0617              S3C2412_SLPCON_IN(6)    |
0618              S3C2412_SLPCON_IN(7)    |
0619              S3C2412_SLPCON_PULL(8)  |
0620              S3C2412_SLPCON_PULL(9)  |
0621              S3C2412_SLPCON_IN(10)   |
0622              S3C2412_SLPCON_PULL(11) |
0623              S3C2412_SLPCON_PULL(12) |
0624              S3C2412_SLPCON_PULL(13) |
0625              S3C2412_SLPCON_IN(14)   |
0626              S3C2412_SLPCON_PULL(15), S3C2412_GPGSLPCON);
0627 
0628     /* Port H sleep */
0629 
0630     __raw_writel(S3C2412_SLPCON_PULL(0) |
0631              S3C2412_SLPCON_PULL(1) |
0632              S3C2412_SLPCON_PULL(2) |
0633              S3C2412_SLPCON_PULL(3) |
0634              S3C2412_SLPCON_PULL(4) |
0635              S3C2412_SLPCON_PULL(5) |
0636              S3C2412_SLPCON_PULL(6) |
0637              S3C2412_SLPCON_IN(7)   |
0638              S3C2412_SLPCON_IN(8)   |
0639              S3C2412_SLPCON_PULL(9) |
0640              S3C2412_SLPCON_IN(10), S3C2412_GPHSLPCON);
0641 
0642     /* initialise the power management now we've setup everything. */
0643 
0644     s3c_pm_init();
0645 
0646     /** TODO - check that this is after the cmdline option! */
0647     s3c_nand_set_platdata(&jive_nand_info);
0648 
0649     gpio_request(S3C2410_GPG(13), "lcm reset");
0650     gpio_direction_output(S3C2410_GPG(13), 0);
0651 
0652     gpio_request_one(S3C2410_GPB(6), GPIOF_OUT_INIT_LOW, NULL);
0653     gpio_free(S3C2410_GPB(6));
0654 
0655     /* Turn off suspend on both USB ports, and switch the
0656      * selectable USB port to USB device mode. */
0657 
0658     s3c2410_modify_misccr(S3C2410_MISCCR_USBHOST |
0659                   S3C2410_MISCCR_USBSUSPND0 |
0660                   S3C2410_MISCCR_USBSUSPND1, 0x0);
0661 
0662     s3c24xx_udc_set_platdata(&jive_udc_cfg);
0663     s3c24xx_fb_set_platdata(&jive_lcd_config);
0664 
0665     spi_register_board_info(jive_spi_devs, ARRAY_SIZE(jive_spi_devs));
0666 
0667     s3c_i2c0_set_platdata(&jive_i2c_cfg);
0668     i2c_register_board_info(0, jive_i2c_devs, ARRAY_SIZE(jive_i2c_devs));
0669 
0670     pm_power_off = jive_power_off;
0671 
0672     gpiod_add_lookup_table(&jive_lcdspi_gpiod_table);
0673     gpiod_add_lookup_table(&jive_wm8750_gpiod_table);
0674     platform_add_devices(jive_devices, ARRAY_SIZE(jive_devices));
0675 }
0676 
0677 MACHINE_START(JIVE, "JIVE")
0678     /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
0679     .atag_offset    = 0x100,
0680     .nr_irqs    = NR_IRQS_S3C2412,
0681     .init_irq   = s3c2412_init_irq,
0682     .map_io     = jive_map_io,
0683     .init_machine   = jive_machine_init,
0684     .init_time  = jive_init_time,
0685 MACHINE_END
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