arm/mach-s3c/irqs-s3c64xx.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* linux/arch/arm/mach-s3c64xx/include/mach/irqs.h
0003  *
0004  * Copyright 2008 Openmoko, Inc.
0005  * Copyright 2008 Simtec Electronics
0006  *      Ben Dooks <ben@simtec.co.uk>
0007  *      http://armlinux.simtec.co.uk/
0008  *
0009  * S3C64XX - IRQ support
0010  */
0011
0012 #ifndef __ASM_MACH_S3C64XX_IRQS_H
0013 #define __ASM_MACH_S3C64XX_IRQS_H __FILE__
0014
0015 /* we keep the first set of CPU IRQs out of the range of
0016  * the ISA space, so that the PC104 has them to itself
0017  * and we don't end up having to do horrible things to the
0018  * standard ISA drivers....
0019  *
0020  * note, since we're using the VICs, our start must be a
0021  * mulitple of 32 to allow the common code to work
0022  */
0023
0024 #define S3C_IRQ_OFFSET  (32)
0025
0026 #define S3C_IRQ(x)  ((x) + S3C_IRQ_OFFSET)
0027
0028 #define IRQ_VIC0_BASE   S3C_IRQ(0)
0029 #define IRQ_VIC1_BASE   S3C_IRQ(32)
0030
0031 /* VIC based IRQs */
0032
0033 #define S3C64XX_IRQ_VIC0(x) (IRQ_VIC0_BASE + (x))
0034 #define S3C64XX_IRQ_VIC1(x) (IRQ_VIC1_BASE + (x))
0035
0036 /* VIC0 */
0037
0038 #define IRQ_EINT0_3     S3C64XX_IRQ_VIC0(0)
0039 #define IRQ_EINT4_11        S3C64XX_IRQ_VIC0(1)
0040 #define IRQ_RTC_TIC     S3C64XX_IRQ_VIC0(2)
0041 #define IRQ_CAMIF_C     S3C64XX_IRQ_VIC0(3)
0042 #define IRQ_CAMIF_P     S3C64XX_IRQ_VIC0(4)
0043 #define IRQ_CAMIF_MC        S3C64XX_IRQ_VIC0(5)
0044 #define IRQ_S3C6410_IIC1    S3C64XX_IRQ_VIC0(5)
0045 #define IRQ_S3C6410_IIS     S3C64XX_IRQ_VIC0(6)
0046 #define IRQ_S3C6400_CAMIF_MP    S3C64XX_IRQ_VIC0(6)
0047 #define IRQ_CAMIF_WE_C      S3C64XX_IRQ_VIC0(7)
0048 #define IRQ_S3C6410_G3D     S3C64XX_IRQ_VIC0(8)
0049 #define IRQ_S3C6400_CAMIF_WE_P  S3C64XX_IRQ_VIC0(8)
0050 #define IRQ_POST0       S3C64XX_IRQ_VIC0(9)
0051 #define IRQ_ROTATOR     S3C64XX_IRQ_VIC0(10)
0052 #define IRQ_2D          S3C64XX_IRQ_VIC0(11)
0053 #define IRQ_TVENC       S3C64XX_IRQ_VIC0(12)
0054 #define IRQ_SCALER      S3C64XX_IRQ_VIC0(13)
0055 #define IRQ_BATF        S3C64XX_IRQ_VIC0(14)
0056 #define IRQ_JPEG        S3C64XX_IRQ_VIC0(15)
0057 #define IRQ_MFC         S3C64XX_IRQ_VIC0(16)
0058 #define IRQ_SDMA0       S3C64XX_IRQ_VIC0(17)
0059 #define IRQ_SDMA1       S3C64XX_IRQ_VIC0(18)
0060 #define IRQ_ARM_DMAERR      S3C64XX_IRQ_VIC0(19)
0061 #define IRQ_ARM_DMA     S3C64XX_IRQ_VIC0(20)
0062 #define IRQ_ARM_DMAS        S3C64XX_IRQ_VIC0(21)
0063 #define IRQ_KEYPAD      S3C64XX_IRQ_VIC0(22)
0064 #define IRQ_TIMER0_VIC      S3C64XX_IRQ_VIC0(23)
0065 #define IRQ_TIMER1_VIC      S3C64XX_IRQ_VIC0(24)
0066 #define IRQ_TIMER2_VIC      S3C64XX_IRQ_VIC0(25)
0067 #define IRQ_WDT         S3C64XX_IRQ_VIC0(26)
0068 #define IRQ_TIMER3_VIC      S3C64XX_IRQ_VIC0(27)
0069 #define IRQ_TIMER4_VIC      S3C64XX_IRQ_VIC0(28)
0070 #define IRQ_LCD_FIFO        S3C64XX_IRQ_VIC0(29)
0071 #define IRQ_LCD_VSYNC       S3C64XX_IRQ_VIC0(30)
0072 #define IRQ_LCD_SYSTEM      S3C64XX_IRQ_VIC0(31)
0073
0074 /* VIC1 */
0075
0076 #define IRQ_EINT12_19       S3C64XX_IRQ_VIC1(0)
0077 #define IRQ_EINT20_27       S3C64XX_IRQ_VIC1(1)
0078 #define IRQ_PCM0        S3C64XX_IRQ_VIC1(2)
0079 #define IRQ_PCM1        S3C64XX_IRQ_VIC1(3)
0080 #define IRQ_AC97        S3C64XX_IRQ_VIC1(4)
0081 #define IRQ_UART0       S3C64XX_IRQ_VIC1(5)
0082 #define IRQ_UART1       S3C64XX_IRQ_VIC1(6)
0083 #define IRQ_UART2       S3C64XX_IRQ_VIC1(7)
0084 #define IRQ_UART3       S3C64XX_IRQ_VIC1(8)
0085 #define IRQ_DMA0        S3C64XX_IRQ_VIC1(9)
0086 #define IRQ_DMA1        S3C64XX_IRQ_VIC1(10)
0087 #define IRQ_ONENAND0        S3C64XX_IRQ_VIC1(11)
0088 #define IRQ_ONENAND1        S3C64XX_IRQ_VIC1(12)
0089 #define IRQ_NFC         S3C64XX_IRQ_VIC1(13)
0090 #define IRQ_CFCON       S3C64XX_IRQ_VIC1(14)
0091 #define IRQ_USBH        S3C64XX_IRQ_VIC1(15)
0092 #define IRQ_SPI0        S3C64XX_IRQ_VIC1(16)
0093 #define IRQ_SPI1        S3C64XX_IRQ_VIC1(17)
0094 #define IRQ_IIC         S3C64XX_IRQ_VIC1(18)
0095 #define IRQ_HSItx       S3C64XX_IRQ_VIC1(19)
0096 #define IRQ_HSIrx       S3C64XX_IRQ_VIC1(20)
0097 #define IRQ_RESERVED        S3C64XX_IRQ_VIC1(21)
0098 #define IRQ_MSM         S3C64XX_IRQ_VIC1(22)
0099 #define IRQ_HOSTIF      S3C64XX_IRQ_VIC1(23)
0100 #define IRQ_HSMMC0      S3C64XX_IRQ_VIC1(24)
0101 #define IRQ_HSMMC1      S3C64XX_IRQ_VIC1(25)
0102 #define IRQ_HSMMC2      IRQ_SPI1    /* shared with SPI1 */
0103 #define IRQ_OTG         S3C64XX_IRQ_VIC1(26)
0104 #define IRQ_IRDA        S3C64XX_IRQ_VIC1(27)
0105 #define IRQ_RTC_ALARM       S3C64XX_IRQ_VIC1(28)
0106 #define IRQ_SEC         S3C64XX_IRQ_VIC1(29)
0107 #define IRQ_PENDN       S3C64XX_IRQ_VIC1(30)
0108 #define IRQ_TC          IRQ_PENDN
0109 #define IRQ_ADC         S3C64XX_IRQ_VIC1(31)
0110
0111 /* compatibility for device defines */
0112
0113 #define IRQ_IIC1        IRQ_S3C6410_IIC1
0114
0115 /* Since the IRQ_EINT(x) are a linear mapping on current s3c64xx series
0116  * we just defined them as an IRQ_EINT(x) macro from S3C_IRQ_EINT_BASE
0117  * which we place after the pair of VICs. */
0118
0119 #define S3C_IRQ_EINT_BASE   S3C_IRQ(64+5)
0120
0121 #define S3C_EINT(x)     ((x) + S3C_IRQ_EINT_BASE)
0122 #define IRQ_EINT(x)     S3C_EINT(x)
0123 #define IRQ_EINT_BIT(x)     ((x) - S3C_EINT(0))
0124
0125 /* Next the external interrupt groups. These are similar to the IRQ_EINT(x)
0126  * that they are sourced from the GPIO pins but with a different scheme for
0127  * priority and source indication.
0128  *
0129  * The IRQ_EINT(x) can be thought of as 'group 0' of the available GPIO
0130  * interrupts, but for historical reasons they are kept apart from these
0131  * next interrupts.
0132  *
0133  * Use IRQ_EINT_GROUP(group, offset) to get the number for use in the
0134  * machine specific support files.
0135  */
0136
0137 #define IRQ_EINT_GROUP1_NR  (15)
0138 #define IRQ_EINT_GROUP2_NR  (8)
0139 #define IRQ_EINT_GROUP3_NR  (5)
0140 #define IRQ_EINT_GROUP4_NR  (14)
0141 #define IRQ_EINT_GROUP5_NR  (7)
0142 #define IRQ_EINT_GROUP6_NR  (10)
0143 #define IRQ_EINT_GROUP7_NR  (16)
0144 #define IRQ_EINT_GROUP8_NR  (15)
0145 #define IRQ_EINT_GROUP9_NR  (9)
0146
0147 #define IRQ_EINT_GROUP_BASE S3C_EINT(28)
0148 #define IRQ_EINT_GROUP1_BASE    (IRQ_EINT_GROUP_BASE + 0x00)
0149 #define IRQ_EINT_GROUP2_BASE    (IRQ_EINT_GROUP1_BASE + IRQ_EINT_GROUP1_NR)
0150 #define IRQ_EINT_GROUP3_BASE    (IRQ_EINT_GROUP2_BASE + IRQ_EINT_GROUP2_NR)
0151 #define IRQ_EINT_GROUP4_BASE    (IRQ_EINT_GROUP3_BASE + IRQ_EINT_GROUP3_NR)
0152 #define IRQ_EINT_GROUP5_BASE    (IRQ_EINT_GROUP4_BASE + IRQ_EINT_GROUP4_NR)
0153 #define IRQ_EINT_GROUP6_BASE    (IRQ_EINT_GROUP5_BASE + IRQ_EINT_GROUP5_NR)
0154 #define IRQ_EINT_GROUP7_BASE    (IRQ_EINT_GROUP6_BASE + IRQ_EINT_GROUP6_NR)
0155 #define IRQ_EINT_GROUP8_BASE    (IRQ_EINT_GROUP7_BASE + IRQ_EINT_GROUP7_NR)
0156 #define IRQ_EINT_GROUP9_BASE    (IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR)
0157
0158 #define IRQ_EINT_GROUP(group, no)   (IRQ_EINT_GROUP##group##_BASE + (no))
0159
0160 /* Some boards have their own IRQs behind this */
0161 #define IRQ_BOARD_START (IRQ_EINT_GROUP9_BASE + IRQ_EINT_GROUP9_NR + 1)
0162
0163 /* Set the default nr_irqs, boards can override if necessary */
0164 #define S3C64XX_NR_IRQS IRQ_BOARD_START
0165
0166 /* Compatibility */
0167
0168 #define IRQ_ONENAND IRQ_ONENAND0
0169 #define IRQ_I2S0    IRQ_S3C6410_IIS
0170
0171 #endif /* __ASM_MACH_S3C64XX_IRQS_H */
0172