arm/mach-s3c/cpufreq-utils-s3c24xx.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 //
0003 // Copyright (c) 2009 Simtec Electronics
0004 //  http://armlinux.simtec.co.uk/
0005 //  Ben Dooks <ben@simtec.co.uk>
0006 //
0007 // S3C24XX CPU Frequency scaling - utils for S3C2410/S3C2440/S3C2442
0008
0009 #include <linux/kernel.h>
0010 #include <linux/errno.h>
0011 #include <linux/cpufreq.h>
0012 #include <linux/io.h>
0013 #include <linux/clk.h>
0014
0015 #include "map.h"
0016 #include "regs-clock.h"
0017
0018 #include <linux/soc/samsung/s3c-cpufreq-core.h>
0019
0020 #include "regs-mem-s3c24xx.h"
0021
0022 /**
0023  * s3c2410_cpufreq_setrefresh - set SDRAM refresh value
0024  * @cfg: The frequency configuration
0025  *
0026  * Set the SDRAM refresh value appropriately for the configured
0027  * frequency.
0028  */
0029 void s3c2410_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg)
0030 {
0031     struct s3c_cpufreq_board *board = cfg->board;
0032     unsigned long refresh;
0033     unsigned long refval;
0034
0035     /* Reduce both the refresh time (in ns) and the frequency (in MHz)
0036      * down to ensure that we do not overflow 32 bit numbers.
0037      *
0038      * This should work for HCLK up to 133MHz and refresh period up
0039      * to 30usec.
0040      */
0041
0042     refresh = (cfg->freq.hclk / 100) * (board->refresh / 10);
0043     refresh = DIV_ROUND_UP(refresh, (1000 * 1000)); /* apply scale  */
0044     refresh = (1 << 11) + 1 - refresh;
0045
0046     s3c_freq_dbg("%s: refresh value %lu\n", __func__, refresh);
0047
0048     refval = __raw_readl(S3C2410_REFRESH);
0049     refval &= ~((1 << 12) - 1);
0050     refval |= refresh;
0051     __raw_writel(refval, S3C2410_REFRESH);
0052 }
0053
0054 /**
0055  * s3c2410_set_fvco - set the PLL value
0056  * @cfg: The frequency configuration
0057  */
0058 void s3c2410_set_fvco(struct s3c_cpufreq_config *cfg)
0059 {
0060     if (!IS_ERR(cfg->mpll))
0061         clk_set_rate(cfg->mpll, cfg->pll.frequency);
0062 }
0063
0064 #if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442)
0065 u32 s3c2440_read_camdivn(void)
0066 {
0067     return __raw_readl(S3C2440_CAMDIVN);
0068 }
0069
0070 void s3c2440_write_camdivn(u32 camdiv)
0071 {
0072     __raw_writel(camdiv, S3C2440_CAMDIVN);
0073 }
0074 #endif
0075
0076 u32 s3c24xx_read_clkdivn(void)
0077 {
0078     return __raw_readl(S3C2410_CLKDIVN);
0079 }
0080
0081 void s3c24xx_write_clkdivn(u32 clkdiv)
0082 {
0083     __raw_writel(clkdiv, S3C2410_CLKDIVN);
0084 }
0085
0086 u32 s3c24xx_read_mpllcon(void)
0087 {
0088     return __raw_readl(S3C2410_MPLLCON);
0089 }
0090
0091 void s3c24xx_write_locktime(u32 locktime)
0092 {
0093     return __raw_writel(locktime, S3C2410_LOCKTIME);
0094 }