arm/mach-s3c/bast.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright (c) 2003-2004 Simtec Electronics
0004  *  Ben Dooks <ben@simtec.co.uk>
0005  *
0006  * BAST - CPLD control constants
0007  * BAST - IRQ Number definitions
0008  * BAST - Memory map definitions
0009  */
0010
0011 #ifndef __MACH_S3C24XX_BAST_H
0012 #define __MACH_S3C24XX_BAST_H __FILE__
0013
0014 /* CTRL1 - Audio LR routing */
0015
0016 #define BAST_CPLD_CTRL1_LRCOFF      (0x00)
0017 #define BAST_CPLD_CTRL1_LRCADC      (0x01)
0018 #define BAST_CPLD_CTRL1_LRCDAC      (0x02)
0019 #define BAST_CPLD_CTRL1_LRCARM      (0x03)
0020 #define BAST_CPLD_CTRL1_LRMASK      (0x03)
0021
0022 /* CTRL2 - NAND WP control, IDE Reset assert/check */
0023
0024 #define BAST_CPLD_CTRL2_WNAND       (0x04)
0025 #define BAST_CPLD_CTLR2_IDERST      (0x08)
0026
0027 /* CTRL3 - rom write control, CPLD identity */
0028
0029 #define BAST_CPLD_CTRL3_IDMASK      (0x0e)
0030 #define BAST_CPLD_CTRL3_ROMWEN      (0x01)
0031
0032 /* CTRL4 - 8bit LCD interface control/status */
0033
0034 #define BAST_CPLD_CTRL4_LLAT        (0x01)
0035 #define BAST_CPLD_CTRL4_LCDRW       (0x02)
0036 #define BAST_CPLD_CTRL4_LCDCMD      (0x04)
0037 #define BAST_CPLD_CTRL4_LCDE2       (0x01)
0038
0039 /* CTRL5 - DMA routing */
0040
0041 #define BAST_CPLD_DMA0_PRIIDE       (0)
0042 #define BAST_CPLD_DMA0_SECIDE       (1)
0043 #define BAST_CPLD_DMA0_ISA15        (2)
0044 #define BAST_CPLD_DMA0_ISA36        (3)
0045
0046 #define BAST_CPLD_DMA1_PRIIDE       (0 << 2)
0047 #define BAST_CPLD_DMA1_SECIDE       (1 << 2)
0048 #define BAST_CPLD_DMA1_ISA15        (2 << 2)
0049 #define BAST_CPLD_DMA1_ISA36        (3 << 2)
0050
0051 /* irq numbers to onboard peripherals */
0052
0053 #define BAST_IRQ_USBOC          IRQ_EINT18
0054 #define BAST_IRQ_IDE0           IRQ_EINT16
0055 #define BAST_IRQ_IDE1           IRQ_EINT17
0056 #define BAST_IRQ_PCSERIAL1      IRQ_EINT15
0057 #define BAST_IRQ_PCSERIAL2      IRQ_EINT14
0058 #define BAST_IRQ_PCPARALLEL     IRQ_EINT13
0059 #define BAST_IRQ_ASIX           IRQ_EINT11
0060 #define BAST_IRQ_DM9000         IRQ_EINT10
0061 #define BAST_IRQ_ISA            IRQ_EINT9
0062 #define BAST_IRQ_SMALERT        IRQ_EINT8
0063
0064 /* map */
0065
0066 /*
0067  * ok, we've used up to 0x13000000, now we need to find space for the
0068  * peripherals that live in the nGCS[x] areas, which are quite numerous
0069  * in their space. We also have the board's CPLD to find register space
0070  * for.
0071  */
0072
0073 #define BAST_IOADDR(x)          (S3C2410_ADDR((x) + 0x01300000))
0074
0075 /* we put the CPLD registers next, to get them out of the way */
0076
0077 #define BAST_VA_CTRL1           BAST_IOADDR(0x00000000)
0078 #define BAST_PA_CTRL1           (S3C2410_CS5 | 0x7800000)
0079
0080 #define BAST_VA_CTRL2           BAST_IOADDR(0x00100000)
0081 #define BAST_PA_CTRL2           (S3C2410_CS1 | 0x6000000)
0082
0083 #define BAST_VA_CTRL3           BAST_IOADDR(0x00200000)
0084 #define BAST_PA_CTRL3           (S3C2410_CS1 | 0x6800000)
0085
0086 #define BAST_VA_CTRL4           BAST_IOADDR(0x00300000)
0087 #define BAST_PA_CTRL4           (S3C2410_CS1 | 0x7000000)
0088
0089 /* next, we have the PC104 ISA interrupt registers */
0090
0091 #define BAST_PA_PC104_IRQREQ        (S3C2410_CS5 | 0x6000000)
0092 #define BAST_VA_PC104_IRQREQ        BAST_IOADDR(0x00400000)
0093
0094 #define BAST_PA_PC104_IRQRAW        (S3C2410_CS5 | 0x6800000)
0095 #define BAST_VA_PC104_IRQRAW        BAST_IOADDR(0x00500000)
0096
0097 #define BAST_PA_PC104_IRQMASK       (S3C2410_CS5 | 0x7000000)
0098 #define BAST_VA_PC104_IRQMASK       BAST_IOADDR(0x00600000)
0099
0100 #define BAST_PA_LCD_RCMD1       (0x8800000)
0101 #define BAST_VA_LCD_RCMD1       BAST_IOADDR(0x00700000)
0102
0103 #define BAST_PA_LCD_WCMD1       (0x8000000)
0104 #define BAST_VA_LCD_WCMD1       BAST_IOADDR(0x00800000)
0105
0106 #define BAST_PA_LCD_RDATA1      (0x9800000)
0107 #define BAST_VA_LCD_RDATA1      BAST_IOADDR(0x00900000)
0108
0109 #define BAST_PA_LCD_WDATA1      (0x9000000)
0110 #define BAST_VA_LCD_WDATA1      BAST_IOADDR(0x00A00000)
0111
0112 #define BAST_PA_LCD_RCMD2       (0xA800000)
0113 #define BAST_VA_LCD_RCMD2       BAST_IOADDR(0x00B00000)
0114
0115 #define BAST_PA_LCD_WCMD2       (0xA000000)
0116 #define BAST_VA_LCD_WCMD2       BAST_IOADDR(0x00C00000)
0117
0118 #define BAST_PA_LCD_RDATA2      (0xB800000)
0119 #define BAST_VA_LCD_RDATA2      BAST_IOADDR(0x00D00000)
0120
0121 #define BAST_PA_LCD_WDATA2      (0xB000000)
0122 #define BAST_VA_LCD_WDATA2      BAST_IOADDR(0x00E00000)
0123
0124
0125 /*
0126  * 0xE0000000 contains the IO space that is split by speed and
0127  * whether the access is for 8 or 16bit IO... this ensures that
0128  * the correct access is made
0129  *
0130  * 0x10000000 of space, partitioned as so:
0131  *
0132  * 0x00000000 to 0x04000000  8bit,  slow
0133  * 0x04000000 to 0x08000000  16bit, slow
0134  * 0x08000000 to 0x0C000000  16bit, net
0135  * 0x0C000000 to 0x10000000  16bit, fast
0136  *
0137  * each of these spaces has the following in:
0138  *
0139  * 0x00000000 to 0x01000000 16MB ISA IO space
0140  * 0x01000000 to 0x02000000 16MB ISA memory space
0141  * 0x02000000 to 0x02100000 1MB  IDE primary channel
0142  * 0x02100000 to 0x02200000 1MB  IDE primary channel aux
0143  * 0x02200000 to 0x02400000 1MB  IDE secondary channel
0144  * 0x02300000 to 0x02400000 1MB  IDE secondary channel aux
0145  * 0x02400000 to 0x02500000 1MB  ASIX ethernet controller
0146  * 0x02500000 to 0x02600000 1MB  Davicom DM9000 ethernet controller
0147  * 0x02600000 to 0x02700000 1MB  PC SuperIO controller
0148  *
0149  * the phyiscal layout of the zones are:
0150  *  nGCS2 - 8bit, slow
0151  *  nGCS3 - 16bit, slow
0152  *  nGCS4 - 16bit, net
0153  *  nGCS5 - 16bit, fast
0154  */
0155
0156 #define BAST_VA_MULTISPACE      (0xE0000000)
0157
0158 #define BAST_VA_ISAIO           (BAST_VA_MULTISPACE + 0x00000000)
0159 #define BAST_VA_ISAMEM          (BAST_VA_MULTISPACE + 0x01000000)
0160 #define BAST_VA_IDEPRI          (BAST_VA_MULTISPACE + 0x02000000)
0161 #define BAST_VA_IDEPRIAUX       (BAST_VA_MULTISPACE + 0x02100000)
0162 #define BAST_VA_IDESEC          (BAST_VA_MULTISPACE + 0x02200000)
0163 #define BAST_VA_IDESECAUX       (BAST_VA_MULTISPACE + 0x02300000)
0164 #define BAST_VA_ASIXNET         (BAST_VA_MULTISPACE + 0x02400000)
0165 #define BAST_VA_DM9000          (BAST_VA_MULTISPACE + 0x02500000)
0166 #define BAST_VA_SUPERIO         (BAST_VA_MULTISPACE + 0x02600000)
0167
0168 #define BAST_VAM_CS2            (0x00000000)
0169 #define BAST_VAM_CS3            (0x04000000)
0170 #define BAST_VAM_CS4            (0x08000000)
0171 #define BAST_VAM_CS5            (0x0C000000)
0172
0173 /* physical offset addresses for the peripherals */
0174
0175 #define BAST_PA_ISAIO           (0x00000000)
0176 #define BAST_PA_ASIXNET         (0x01000000)
0177 #define BAST_PA_SUPERIO         (0x01800000)
0178 #define BAST_PA_IDEPRI          (0x02000000)
0179 #define BAST_PA_IDEPRIAUX       (0x02800000)
0180 #define BAST_PA_IDESEC          (0x03000000)
0181 #define BAST_PA_IDESECAUX       (0x03800000)
0182 #define BAST_PA_ISAMEM          (0x04000000)
0183 #define BAST_PA_DM9000          (0x05000000)
0184
0185 /* some configurations for the peripherals */
0186
0187 #define BAST_PCSIO          (BAST_VA_SUPERIO + BAST_VAM_CS2)
0188
0189 #define BAST_ASIXNET_CS         BAST_VAM_CS5
0190 #define BAST_DM9000_CS          BAST_VAM_CS4
0191
0192 #define BAST_IDE_CS S3C2410_CS5
0193
0194 #endif /* __MACH_S3C24XX_BAST_H */