arm/mach-s3c/anubis.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright (c) 2005 Simtec Electronics
0004  *  http://www.simtec.co.uk/products/
0005  *  Ben Dooks <ben@simtec.co.uk>
0006  *
0007  * ANUBIS - CPLD control constants
0008  * ANUBIS - IRQ Number definitions
0009  * ANUBIS - Memory map definitions
0010  */
0011
0012 #ifndef __MACH_S3C24XX_ANUBIS_H
0013 #define __MACH_S3C24XX_ANUBIS_H __FILE__
0014
0015 /* CTRL2 - NAND WP control, IDE Reset assert/check */
0016
0017 #define ANUBIS_CTRL1_NANDSEL        (0x3)
0018
0019 /* IDREG - revision */
0020
0021 #define ANUBIS_IDREG_REVMASK        (0x7)
0022
0023 /* irq */
0024
0025 #define ANUBIS_IRQ_IDE0         IRQ_EINT2
0026 #define ANUBIS_IRQ_IDE1         IRQ_EINT3
0027 #define ANUBIS_IRQ_ASIX         IRQ_EINT1
0028
0029 /* map */
0030
0031 /* start peripherals off after the S3C2410 */
0032
0033 #define ANUBIS_IOADDR(x)        (S3C2410_ADDR((x) + 0x01800000))
0034
0035 #define ANUBIS_PA_CPLD          (S3C2410_CS1 | (1<<26))
0036
0037 /* we put the CPLD registers next, to get them out of the way */
0038
0039 #define ANUBIS_VA_CTRL1         ANUBIS_IOADDR(0x00000000)
0040 #define ANUBIS_PA_CTRL1         ANUBIS_PA_CPLD
0041
0042 #define ANUBIS_VA_IDREG         ANUBIS_IOADDR(0x00300000)
0043 #define ANUBIS_PA_IDREG         (ANUBIS_PA_CPLD + (3 << 23))
0044
0045 #define ANUBIS_IDEPRI           ANUBIS_IOADDR(0x01000000)
0046 #define ANUBIS_IDEPRIAUX        ANUBIS_IOADDR(0x01100000)
0047 #define ANUBIS_IDESEC           ANUBIS_IOADDR(0x01200000)
0048 #define ANUBIS_IDESECAUX        ANUBIS_IOADDR(0x01300000)
0049
0050 #endif /* __MACH_S3C24XX_ANUBIS_H */