arm/mach-rockchip/sleep.S

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
0004  * Author: Tony Xie <tony.xie@rock-chips.com>
0005  */
0006
0007 #include <linux/linkage.h>
0008 #include <asm/assembler.h>
0009 #include <asm/memory.h>
0010
0011 .data
0012 /*
0013  * this code will be copied from
0014  * ddr to sram for system resumeing.
0015  * so it is ".data section".
0016  */
0017     .align  2
0018
0019 ENTRY(rockchip_slp_cpu_resume)
0020     setmode PSR_I_BIT | PSR_F_BIT | SVC_MODE, r1  @ set svc, irqs off
0021     mrc p15, 0, r1, c0, c0, 5
0022     and r1, r1, #0xf
0023     cmp r1, #0
0024     /* olny cpu0 can continue to run, the others is halt here */
0025     beq cpu0run
0026 secondary_loop:
0027     wfe
0028     b   secondary_loop
0029 cpu0run:
0030     ldr r3, rkpm_bootdata_l2ctlr_f
0031     cmp r3, #0
0032     beq sp_set
0033     ldr r3, rkpm_bootdata_l2ctlr
0034     mcr p15, 1, r3, c9, c0, 2
0035 sp_set:
0036     ldr sp, rkpm_bootdata_cpusp
0037     ldr r1, rkpm_bootdata_cpu_code
0038     bx  r1
0039 ENDPROC(rockchip_slp_cpu_resume)
0040
0041 /* Parameters filled in by the kernel */
0042
0043 /* Flag for whether to restore L2CTLR on resume */
0044     .global rkpm_bootdata_l2ctlr_f
0045 rkpm_bootdata_l2ctlr_f:
0046     .long 0
0047
0048 /* Saved L2CTLR to restore on resume */
0049     .global rkpm_bootdata_l2ctlr
0050 rkpm_bootdata_l2ctlr:
0051     .long 0
0052
0053 /* CPU resume SP addr */
0054     .globl rkpm_bootdata_cpusp
0055 rkpm_bootdata_cpusp:
0056     .long 0
0057
0058 /* CPU resume function (physical address) */
0059     .globl rkpm_bootdata_cpu_code
0060 rkpm_bootdata_cpu_code:
0061     .long 0
0062
0063 ENTRY(rk3288_bootram_sz)
0064         .word   . - rockchip_slp_cpu_resume