arm/mach-rockchip/pm.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
0004  * Author: Tony Xie <tony.xie@rock-chips.com>
0005  */
0006
0007 #ifndef __MACH_ROCKCHIP_PM_H
0008 #define __MACH_ROCKCHIP_PM_H
0009
0010 extern unsigned long rkpm_bootdata_cpusp;
0011 extern unsigned long rkpm_bootdata_cpu_code;
0012 extern unsigned long rkpm_bootdata_l2ctlr_f;
0013 extern unsigned long rkpm_bootdata_l2ctlr;
0014 extern unsigned long rkpm_bootdata_ddr_code;
0015 extern unsigned long rkpm_bootdata_ddr_data;
0016 extern unsigned long rk3288_bootram_sz;
0017
0018 void rockchip_slp_cpu_resume(void);
0019 #ifdef CONFIG_PM_SLEEP
0020 void __init rockchip_suspend_init(void);
0021 #else
0022 static inline void rockchip_suspend_init(void)
0023 {
0024 }
0025 #endif
0026
0027 /****** following is rk3288 defined **********/
0028 #define RK3288_PMU_WAKEUP_CFG0      0x00
0029 #define RK3288_PMU_WAKEUP_CFG1      0x04
0030 #define RK3288_PMU_PWRMODE_CON      0x18
0031 #define RK3288_PMU_OSC_CNT      0x20
0032 #define RK3288_PMU_PLL_CNT      0x24
0033 #define RK3288_PMU_STABL_CNT        0x28
0034 #define RK3288_PMU_DDR0IO_PWRON_CNT 0x2c
0035 #define RK3288_PMU_DDR1IO_PWRON_CNT 0x30
0036 #define RK3288_PMU_CORE_PWRDWN_CNT  0x34
0037 #define RK3288_PMU_CORE_PWRUP_CNT   0x38
0038 #define RK3288_PMU_GPU_PWRDWN_CNT   0x3c
0039 #define RK3288_PMU_GPU_PWRUP_CNT    0x40
0040 #define RK3288_PMU_WAKEUP_RST_CLR_CNT   0x44
0041 #define RK3288_PMU_PWRMODE_CON1     0x90
0042
0043 #define RK3288_SGRF_SOC_CON0        (0x0000)
0044 #define RK3288_SGRF_FAST_BOOT_ADDR  (0x0120)
0045 #define SGRF_PCLK_WDT_GATE      BIT(6)
0046 #define SGRF_PCLK_WDT_GATE_WRITE    BIT(22)
0047 #define SGRF_FAST_BOOT_EN       BIT(8)
0048 #define SGRF_FAST_BOOT_EN_WRITE     BIT(24)
0049
0050 #define RK3288_SGRF_CPU_CON0        (0x40)
0051 #define SGRF_DAPDEVICEEN        BIT(0)
0052 #define SGRF_DAPDEVICEEN_WRITE      BIT(16)
0053
0054 /* PMU_WAKEUP_CFG1 bits */
0055 #define PMU_ARMINT_WAKEUP_EN        BIT(0)
0056 #define PMU_GPIOINT_WAKEUP_EN       BIT(3)
0057
0058 enum rk3288_pwr_mode_con {
0059     PMU_PWR_MODE_EN = 0,
0060     PMU_CLK_CORE_SRC_GATE_EN,
0061     PMU_GLOBAL_INT_DISABLE,
0062     PMU_L2FLUSH_EN,
0063     PMU_BUS_PD_EN,
0064     PMU_A12_0_PD_EN,
0065     PMU_SCU_EN,
0066     PMU_PLL_PD_EN,
0067     PMU_CHIP_PD_EN, /* POWER OFF PIN ENABLE */
0068     PMU_PWROFF_COMB,
0069     PMU_ALIVE_USE_LF,
0070     PMU_PMU_USE_LF,
0071     PMU_OSC_24M_DIS,
0072     PMU_INPUT_CLAMP_EN,
0073     PMU_WAKEUP_RESET_EN,
0074     PMU_SREF0_ENTER_EN,
0075     PMU_SREF1_ENTER_EN,
0076     PMU_DDR0IO_RET_EN,
0077     PMU_DDR1IO_RET_EN,
0078     PMU_DDR0_GATING_EN,
0079     PMU_DDR1_GATING_EN,
0080     PMU_DDR0IO_RET_DE_REQ,
0081     PMU_DDR1IO_RET_DE_REQ
0082 };
0083
0084 enum rk3288_pwr_mode_con1 {
0085     PMU_CLR_BUS = 0,
0086     PMU_CLR_CORE,
0087     PMU_CLR_CPUP,
0088     PMU_CLR_ALIVE,
0089     PMU_CLR_DMA,
0090     PMU_CLR_PERI,
0091     PMU_CLR_GPU,
0092     PMU_CLR_VIDEO,
0093     PMU_CLR_HEVC,
0094     PMU_CLR_VIO,
0095 };
0096
0097 #endif /* __MACH_ROCKCHIP_PM_H */