arm/mach-rockchip/pm.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
0004  * Author: Tony Xie <tony.xie@rock-chips.com>
0005  */
0006
0007 #include <linux/init.h>
0008 #include <linux/io.h>
0009 #include <linux/kernel.h>
0010 #include <linux/of.h>
0011 #include <linux/of_address.h>
0012 #include <linux/regmap.h>
0013 #include <linux/suspend.h>
0014 #include <linux/mfd/syscon.h>
0015 #include <linux/regulator/machine.h>
0016
0017 #include <asm/cacheflush.h>
0018 #include <asm/tlbflush.h>
0019 #include <asm/suspend.h>
0020
0021 #include "pm.h"
0022
0023 /* These enum are option of low power mode */
0024 enum {
0025     ROCKCHIP_ARM_OFF_LOGIC_NORMAL = 0,
0026     ROCKCHIP_ARM_OFF_LOGIC_DEEP = 1,
0027 };
0028
0029 struct rockchip_pm_data {
0030     const struct platform_suspend_ops *ops;
0031     int (*init)(struct device_node *np);
0032 };
0033
0034 static void __iomem *rk3288_bootram_base;
0035 static phys_addr_t rk3288_bootram_phy;
0036
0037 static struct regmap *pmu_regmap;
0038 static struct regmap *sgrf_regmap;
0039 static struct regmap *grf_regmap;
0040
0041 static u32 rk3288_pmu_pwr_mode_con;
0042 static u32 rk3288_sgrf_soc_con0;
0043 static u32 rk3288_sgrf_cpu_con0;
0044
0045 static inline u32 rk3288_l2_config(void)
0046 {
0047     u32 l2ctlr;
0048
0049     asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (l2ctlr));
0050     return l2ctlr;
0051 }
0052
0053 static void __init rk3288_config_bootdata(void)
0054 {
0055     rkpm_bootdata_cpusp = rk3288_bootram_phy + (SZ_4K - 8);
0056     rkpm_bootdata_cpu_code = __pa_symbol(cpu_resume);
0057
0058     rkpm_bootdata_l2ctlr_f  = 1;
0059     rkpm_bootdata_l2ctlr = rk3288_l2_config();
0060 }
0061
0062 #define GRF_UOC0_CON0           0x320
0063 #define GRF_UOC1_CON0           0x334
0064 #define GRF_UOC2_CON0           0x348
0065 #define GRF_SIDDQ           BIT(13)
0066
0067 static bool rk3288_slp_disable_osc(void)
0068 {
0069     static const u32 reg_offset[] = { GRF_UOC0_CON0, GRF_UOC1_CON0,
0070                       GRF_UOC2_CON0 };
0071     u32 reg, i;
0072
0073     /*
0074      * if any usb phy is still on(GRF_SIDDQ==0), that means we need the
0075      * function of usb wakeup, so do not switch to 32khz, since the usb phy
0076      * clk does not connect to 32khz osc
0077      */
0078     for (i = 0; i < ARRAY_SIZE(reg_offset); i++) {
0079         regmap_read(grf_regmap, reg_offset[i], &reg);
0080         if (!(reg & GRF_SIDDQ))
0081             return false;
0082     }
0083
0084     return true;
0085 }
0086
0087 static void rk3288_slp_mode_set(int level)
0088 {
0089     u32 mode_set, mode_set1;
0090     bool osc_disable = rk3288_slp_disable_osc();
0091
0092     regmap_read(sgrf_regmap, RK3288_SGRF_CPU_CON0, &rk3288_sgrf_cpu_con0);
0093     regmap_read(sgrf_regmap, RK3288_SGRF_SOC_CON0, &rk3288_sgrf_soc_con0);
0094
0095     regmap_read(pmu_regmap, RK3288_PMU_PWRMODE_CON,
0096             &rk3288_pmu_pwr_mode_con);
0097
0098     /*
0099      * SGRF_FAST_BOOT_EN - system to boot from FAST_BOOT_ADDR
0100      * PCLK_WDT_GATE - disable WDT during suspend.
0101      */
0102     regmap_write(sgrf_regmap, RK3288_SGRF_SOC_CON0,
0103              SGRF_PCLK_WDT_GATE | SGRF_FAST_BOOT_EN
0104              | SGRF_PCLK_WDT_GATE_WRITE | SGRF_FAST_BOOT_EN_WRITE);
0105
0106     /*
0107      * The dapswjdp can not auto reset before resume, that cause it may
0108      * access some illegal address during resume. Let's disable it before
0109      * suspend, and the MASKROM will enable it back.
0110      */
0111     regmap_write(sgrf_regmap, RK3288_SGRF_CPU_CON0, SGRF_DAPDEVICEEN_WRITE);
0112
0113     /* booting address of resuming system is from this register value */
0114     regmap_write(sgrf_regmap, RK3288_SGRF_FAST_BOOT_ADDR,
0115              rk3288_bootram_phy);
0116
0117     mode_set = BIT(PMU_GLOBAL_INT_DISABLE) | BIT(PMU_L2FLUSH_EN) |
0118            BIT(PMU_SREF0_ENTER_EN) | BIT(PMU_SREF1_ENTER_EN) |
0119            BIT(PMU_DDR0_GATING_EN) | BIT(PMU_DDR1_GATING_EN) |
0120            BIT(PMU_PWR_MODE_EN) | BIT(PMU_CHIP_PD_EN) |
0121            BIT(PMU_SCU_EN);
0122
0123     mode_set1 = BIT(PMU_CLR_CORE) | BIT(PMU_CLR_CPUP);
0124
0125     if (level == ROCKCHIP_ARM_OFF_LOGIC_DEEP) {
0126         /* arm off, logic deep sleep */
0127         mode_set |= BIT(PMU_BUS_PD_EN) | BIT(PMU_PMU_USE_LF) |
0128                 BIT(PMU_DDR1IO_RET_EN) | BIT(PMU_DDR0IO_RET_EN) |
0129                 BIT(PMU_ALIVE_USE_LF) | BIT(PMU_PLL_PD_EN);
0130
0131         if (osc_disable)
0132             mode_set |= BIT(PMU_OSC_24M_DIS);
0133
0134         mode_set1 |= BIT(PMU_CLR_ALIVE) | BIT(PMU_CLR_BUS) |
0135                  BIT(PMU_CLR_PERI) | BIT(PMU_CLR_DMA);
0136
0137         regmap_write(pmu_regmap, RK3288_PMU_WAKEUP_CFG1,
0138                  PMU_ARMINT_WAKEUP_EN);
0139
0140         /*
0141          * In deep suspend we use PMU_PMU_USE_LF to let the rk3288
0142          * switch its main clock supply to the alternative 32kHz
0143          * source. Therefore set 30ms on a 32kHz clock for pmic
0144          * stabilization. Similar 30ms on 24MHz for the other
0145          * mode below.
0146          */
0147         regmap_write(pmu_regmap, RK3288_PMU_STABL_CNT, 32 * 30);
0148
0149         /* only wait for stabilization, if we turned the osc off */
0150         regmap_write(pmu_regmap, RK3288_PMU_OSC_CNT,
0151                      osc_disable ? 32 * 30 : 0);
0152     } else {
0153         /*
0154          * arm off, logic normal
0155          * if pmu_clk_core_src_gate_en is not set,
0156          * wakeup will be error
0157          */
0158         mode_set |= BIT(PMU_CLK_CORE_SRC_GATE_EN);
0159
0160         regmap_write(pmu_regmap, RK3288_PMU_WAKEUP_CFG1,
0161                  PMU_ARMINT_WAKEUP_EN | PMU_GPIOINT_WAKEUP_EN);
0162
0163         /* 30ms on a 24MHz clock for pmic stabilization */
0164         regmap_write(pmu_regmap, RK3288_PMU_STABL_CNT, 24000 * 30);
0165
0166         /* oscillator is still running, so no need to wait */
0167         regmap_write(pmu_regmap, RK3288_PMU_OSC_CNT, 0);
0168     }
0169
0170     regmap_write(pmu_regmap, RK3288_PMU_PWRMODE_CON, mode_set);
0171     regmap_write(pmu_regmap, RK3288_PMU_PWRMODE_CON1, mode_set1);
0172 }
0173
0174 static void rk3288_slp_mode_set_resume(void)
0175 {
0176     regmap_write(sgrf_regmap, RK3288_SGRF_CPU_CON0,
0177              rk3288_sgrf_cpu_con0 | SGRF_DAPDEVICEEN_WRITE);
0178
0179     regmap_write(pmu_regmap, RK3288_PMU_PWRMODE_CON,
0180              rk3288_pmu_pwr_mode_con);
0181
0182     regmap_write(sgrf_regmap, RK3288_SGRF_SOC_CON0,
0183              rk3288_sgrf_soc_con0 | SGRF_PCLK_WDT_GATE_WRITE
0184              | SGRF_FAST_BOOT_EN_WRITE);
0185 }
0186
0187 static int rockchip_lpmode_enter(unsigned long arg)
0188 {
0189     flush_cache_all();
0190
0191     cpu_do_idle();
0192
0193     pr_err("%s: Failed to suspend\n", __func__);
0194
0195     return 1;
0196 }
0197
0198 static int rk3288_suspend_enter(suspend_state_t state)
0199 {
0200     local_fiq_disable();
0201
0202     rk3288_slp_mode_set(ROCKCHIP_ARM_OFF_LOGIC_NORMAL);
0203
0204     cpu_suspend(0, rockchip_lpmode_enter);
0205
0206     rk3288_slp_mode_set_resume();
0207
0208     local_fiq_enable();
0209
0210     return 0;
0211 }
0212
0213 static int rk3288_suspend_prepare(void)
0214 {
0215     return regulator_suspend_prepare(PM_SUSPEND_MEM);
0216 }
0217
0218 static void rk3288_suspend_finish(void)
0219 {
0220     if (regulator_suspend_finish())
0221         pr_err("%s: Suspend finish failed\n", __func__);
0222 }
0223
0224 static int __init rk3288_suspend_init(struct device_node *np)
0225 {
0226     struct device_node *sram_np;
0227     struct resource res;
0228     int ret;
0229
0230     pmu_regmap = syscon_node_to_regmap(np);
0231     if (IS_ERR(pmu_regmap)) {
0232         pr_err("%s: could not find pmu regmap\n", __func__);
0233         return PTR_ERR(pmu_regmap);
0234     }
0235
0236     sgrf_regmap = syscon_regmap_lookup_by_compatible(
0237                 "rockchip,rk3288-sgrf");
0238     if (IS_ERR(sgrf_regmap)) {
0239         pr_err("%s: could not find sgrf regmap\n", __func__);
0240         return PTR_ERR(sgrf_regmap);
0241     }
0242
0243     grf_regmap = syscon_regmap_lookup_by_compatible(
0244                 "rockchip,rk3288-grf");
0245     if (IS_ERR(grf_regmap)) {
0246         pr_err("%s: could not find grf regmap\n", __func__);
0247         return PTR_ERR(grf_regmap);
0248     }
0249
0250     sram_np = of_find_compatible_node(NULL, NULL,
0251                       "rockchip,rk3288-pmu-sram");
0252     if (!sram_np) {
0253         pr_err("%s: could not find bootram dt node\n", __func__);
0254         return -ENODEV;
0255     }
0256
0257     rk3288_bootram_base = of_iomap(sram_np, 0);
0258     if (!rk3288_bootram_base) {
0259         pr_err("%s: could not map bootram base\n", __func__);
0260         of_node_put(sram_np);
0261         return -ENOMEM;
0262     }
0263
0264     ret = of_address_to_resource(sram_np, 0, &res);
0265     if (ret) {
0266         pr_err("%s: could not get bootram phy addr\n", __func__);
0267         of_node_put(sram_np);
0268         return ret;
0269     }
0270     rk3288_bootram_phy = res.start;
0271
0272     of_node_put(sram_np);
0273
0274     rk3288_config_bootdata();
0275
0276     /* copy resume code and data to bootsram */
0277     memcpy(rk3288_bootram_base, rockchip_slp_cpu_resume,
0278            rk3288_bootram_sz);
0279
0280     return 0;
0281 }
0282
0283 static const struct platform_suspend_ops rk3288_suspend_ops = {
0284     .enter   = rk3288_suspend_enter,
0285     .valid   = suspend_valid_only_mem,
0286     .prepare = rk3288_suspend_prepare,
0287     .finish  = rk3288_suspend_finish,
0288 };
0289
0290 static const struct rockchip_pm_data rk3288_pm_data __initconst = {
0291     .ops = &rk3288_suspend_ops,
0292     .init = rk3288_suspend_init,
0293 };
0294
0295 static const struct of_device_id rockchip_pmu_of_device_ids[] __initconst = {
0296     {
0297         .compatible = "rockchip,rk3288-pmu",
0298         .data = &rk3288_pm_data,
0299     },
0300     { /* sentinel */ },
0301 };
0302
0303 void __init rockchip_suspend_init(void)
0304 {
0305     const struct rockchip_pm_data *pm_data;
0306     const struct of_device_id *match;
0307     struct device_node *np;
0308     int ret;
0309
0310     np = of_find_matching_node_and_match(NULL, rockchip_pmu_of_device_ids,
0311                          &match);
0312     if (!match) {
0313         pr_err("Failed to find PMU node\n");
0314         goto out_put;
0315     }
0316     pm_data = (struct rockchip_pm_data *) match->data;
0317
0318     if (pm_data->init) {
0319         ret = pm_data->init(np);
0320
0321         if (ret) {
0322             pr_err("%s: matches init error %d\n", __func__, ret);
0323             goto out_put;
0324         }
0325     }
0326
0327     suspend_set_ops(pm_data->ops);
0328
0329 out_put:
0330     of_node_put(np);
0331 }