arm/mach-rockchip/platsmp.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright (c) 2013 MundoReader S.L.
0004  * Author: Heiko Stuebner <heiko@sntech.de>
0005  */
0006
0007 #include <linux/delay.h>
0008 #include <linux/init.h>
0009 #include <linux/smp.h>
0010 #include <linux/io.h>
0011 #include <linux/of.h>
0012 #include <linux/of_address.h>
0013 #include <linux/regmap.h>
0014 #include <linux/mfd/syscon.h>
0015
0016 #include <linux/reset.h>
0017 #include <linux/cpu.h>
0018 #include <asm/cacheflush.h>
0019 #include <asm/cp15.h>
0020 #include <asm/smp_scu.h>
0021 #include <asm/smp_plat.h>
0022 #include <asm/mach/map.h>
0023
0024 #include "core.h"
0025
0026 static void __iomem *scu_base_addr;
0027 static void __iomem *sram_base_addr;
0028 static int ncores;
0029
0030 #define PMU_PWRDN_CON       0x08
0031 #define PMU_PWRDN_ST        0x0c
0032
0033 #define PMU_PWRDN_SCU       4
0034
0035 static struct regmap *pmu;
0036 static int has_pmu = true;
0037
0038 static int pmu_power_domain_is_on(int pd)
0039 {
0040     u32 val;
0041     int ret;
0042
0043     ret = regmap_read(pmu, PMU_PWRDN_ST, &val);
0044     if (ret < 0)
0045         return ret;
0046
0047     return !(val & BIT(pd));
0048 }
0049
0050 static struct reset_control *rockchip_get_core_reset(int cpu)
0051 {
0052     struct device *dev = get_cpu_device(cpu);
0053     struct device_node *np;
0054
0055     /* The cpu device is only available after the initial core bringup */
0056     if (dev)
0057         np = dev->of_node;
0058     else
0059         np = of_get_cpu_node(cpu, NULL);
0060
0061     return of_reset_control_get_exclusive(np, NULL);
0062 }
0063
0064 static int pmu_set_power_domain(int pd, bool on)
0065 {
0066     u32 val = (on) ? 0 : BIT(pd);
0067     struct reset_control *rstc = rockchip_get_core_reset(pd);
0068     int ret;
0069
0070     if (IS_ERR(rstc) && read_cpuid_part() != ARM_CPU_PART_CORTEX_A9) {
0071         pr_err("%s: could not get reset control for core %d\n",
0072                __func__, pd);
0073         return PTR_ERR(rstc);
0074     }
0075
0076     /*
0077      * We need to soft reset the cpu when we turn off the cpu power domain,
0078      * or else the active processors might be stalled when the individual
0079      * processor is powered down.
0080      */
0081     if (!IS_ERR(rstc) && !on)
0082         reset_control_assert(rstc);
0083
0084     if (has_pmu) {
0085         ret = regmap_update_bits(pmu, PMU_PWRDN_CON, BIT(pd), val);
0086         if (ret < 0) {
0087             pr_err("%s: could not update power domain\n",
0088                    __func__);
0089             return ret;
0090         }
0091
0092         ret = -1;
0093         while (ret != on) {
0094             ret = pmu_power_domain_is_on(pd);
0095             if (ret < 0) {
0096                 pr_err("%s: could not read power domain state\n",
0097                        __func__);
0098                 return ret;
0099             }
0100         }
0101     }
0102
0103     if (!IS_ERR(rstc)) {
0104         if (on)
0105             reset_control_deassert(rstc);
0106         reset_control_put(rstc);
0107     }
0108
0109     return 0;
0110 }
0111
0112 /*
0113  * Handling of CPU cores
0114  */
0115
0116 static int rockchip_boot_secondary(unsigned int cpu, struct task_struct *idle)
0117 {
0118     int ret;
0119
0120     if (!sram_base_addr || (has_pmu && !pmu)) {
0121         pr_err("%s: sram or pmu missing for cpu boot\n", __func__);
0122         return -ENXIO;
0123     }
0124
0125     if (cpu >= ncores) {
0126         pr_err("%s: cpu %d outside maximum number of cpus %d\n",
0127                __func__, cpu, ncores);
0128         return -ENXIO;
0129     }
0130
0131     /* start the core */
0132     ret = pmu_set_power_domain(0 + cpu, true);
0133     if (ret < 0)
0134         return ret;
0135
0136     if (read_cpuid_part() != ARM_CPU_PART_CORTEX_A9) {
0137         /*
0138          * We communicate with the bootrom to active the cpus other
0139          * than cpu0, after a blob of initialize code, they will
0140          * stay at wfe state, once they are activated, they will check
0141          * the mailbox:
0142          * sram_base_addr + 4: 0xdeadbeaf
0143          * sram_base_addr + 8: start address for pc
0144          * The cpu0 need to wait the other cpus other than cpu0 entering
0145          * the wfe state.The wait time is affected by many aspects.
0146          * (e.g: cpu frequency, bootrom frequency, sram frequency, ...)
0147          */
0148         mdelay(1); /* ensure the cpus other than cpu0 to startup */
0149
0150         writel(__pa_symbol(secondary_startup), sram_base_addr + 8);
0151         writel(0xDEADBEAF, sram_base_addr + 4);
0152         dsb_sev();
0153     }
0154
0155     return 0;
0156 }
0157
0158 /**
0159  * rockchip_smp_prepare_sram - populate necessary sram block
0160  * Starting cores execute the code residing at the start of the on-chip sram
0161  * after power-on. Therefore make sure, this sram region is reserved and
0162  * big enough. After this check, copy the trampoline code that directs the
0163  * core to the real startup code in ram into the sram-region.
0164  * @node: mmio-sram device node
0165  */
0166 static int __init rockchip_smp_prepare_sram(struct device_node *node)
0167 {
0168     unsigned int trampoline_sz = &rockchip_secondary_trampoline_end -
0169                         &rockchip_secondary_trampoline;
0170     struct resource res;
0171     unsigned int rsize;
0172     int ret;
0173
0174     ret = of_address_to_resource(node, 0, &res);
0175     if (ret < 0) {
0176         pr_err("%s: could not get address for node %pOF\n",
0177                __func__, node);
0178         return ret;
0179     }
0180
0181     rsize = resource_size(&res);
0182     if (rsize < trampoline_sz) {
0183         pr_err("%s: reserved block with size 0x%x is too small for trampoline size 0x%x\n",
0184                __func__, rsize, trampoline_sz);
0185         return -EINVAL;
0186     }
0187
0188     /* set the boot function for the sram code */
0189     rockchip_boot_fn = __pa_symbol(secondary_startup);
0190
0191     /* copy the trampoline to sram, that runs during startup of the core */
0192     memcpy_toio(sram_base_addr, &rockchip_secondary_trampoline, trampoline_sz);
0193     flush_cache_all();
0194     outer_clean_range(0, trampoline_sz);
0195
0196     dsb_sev();
0197
0198     return 0;
0199 }
0200
0201 static const struct regmap_config rockchip_pmu_regmap_config = {
0202     .name = "rockchip-pmu",
0203     .reg_bits = 32,
0204     .val_bits = 32,
0205     .reg_stride = 4,
0206 };
0207
0208 static int __init rockchip_smp_prepare_pmu(void)
0209 {
0210     struct device_node *node;
0211     void __iomem *pmu_base;
0212
0213     /*
0214      * This function is only called via smp_ops->smp_prepare_cpu().
0215      * That only happens if a "/cpus" device tree node exists
0216      * and has an "enable-method" property that selects the SMP
0217      * operations defined herein.
0218      */
0219     node = of_find_node_by_path("/cpus");
0220
0221     pmu = syscon_regmap_lookup_by_phandle(node, "rockchip,pmu");
0222     of_node_put(node);
0223     if (!IS_ERR(pmu))
0224         return 0;
0225
0226     pmu = syscon_regmap_lookup_by_compatible("rockchip,rk3066-pmu");
0227     if (!IS_ERR(pmu))
0228         return 0;
0229
0230     /* fallback, create our own regmap for the pmu area */
0231     pmu = NULL;
0232     node = of_find_compatible_node(NULL, NULL, "rockchip,rk3066-pmu");
0233     if (!node) {
0234         pr_err("%s: could not find pmu dt node\n", __func__);
0235         return -ENODEV;
0236     }
0237
0238     pmu_base = of_iomap(node, 0);
0239     of_node_put(node);
0240     if (!pmu_base) {
0241         pr_err("%s: could not map pmu registers\n", __func__);
0242         return -ENOMEM;
0243     }
0244
0245     pmu = regmap_init_mmio(NULL, pmu_base, &rockchip_pmu_regmap_config);
0246     if (IS_ERR(pmu)) {
0247         int ret = PTR_ERR(pmu);
0248
0249         iounmap(pmu_base);
0250         pmu = NULL;
0251         pr_err("%s: regmap init failed\n", __func__);
0252         return ret;
0253     }
0254
0255     return 0;
0256 }
0257
0258 static void __init rockchip_smp_prepare_cpus(unsigned int max_cpus)
0259 {
0260     struct device_node *node;
0261     unsigned int i;
0262
0263     node = of_find_compatible_node(NULL, NULL, "rockchip,rk3066-smp-sram");
0264     if (!node) {
0265         pr_err("%s: could not find sram dt node\n", __func__);
0266         return;
0267     }
0268
0269     sram_base_addr = of_iomap(node, 0);
0270     if (!sram_base_addr) {
0271         pr_err("%s: could not map sram registers\n", __func__);
0272         of_node_put(node);
0273         return;
0274     }
0275
0276     if (has_pmu && rockchip_smp_prepare_pmu()) {
0277         of_node_put(node);
0278         return;
0279     }
0280
0281     if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) {
0282         if (rockchip_smp_prepare_sram(node)) {
0283             of_node_put(node);
0284             return;
0285         }
0286
0287         /* enable the SCU power domain */
0288         pmu_set_power_domain(PMU_PWRDN_SCU, true);
0289
0290         of_node_put(node);
0291         node = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
0292         if (!node) {
0293             pr_err("%s: missing scu\n", __func__);
0294             return;
0295         }
0296
0297         scu_base_addr = of_iomap(node, 0);
0298         if (!scu_base_addr) {
0299             pr_err("%s: could not map scu registers\n", __func__);
0300             of_node_put(node);
0301             return;
0302         }
0303
0304         /*
0305          * While the number of cpus is gathered from dt, also get the
0306          * number of cores from the scu to verify this value when
0307          * booting the cores.
0308          */
0309         ncores = scu_get_core_count(scu_base_addr);
0310         pr_err("%s: ncores %d\n", __func__, ncores);
0311
0312         scu_enable(scu_base_addr);
0313     } else {
0314         unsigned int l2ctlr;
0315
0316         asm ("mrc p15, 1, %0, c9, c0, 2\n" : "=r" (l2ctlr));
0317         ncores = ((l2ctlr >> 24) & 0x3) + 1;
0318     }
0319     of_node_put(node);
0320
0321     /* Make sure that all cores except the first are really off */
0322     for (i = 1; i < ncores; i++)
0323         pmu_set_power_domain(0 + i, false);
0324 }
0325
0326 static void __init rk3036_smp_prepare_cpus(unsigned int max_cpus)
0327 {
0328     has_pmu = false;
0329
0330     rockchip_smp_prepare_cpus(max_cpus);
0331 }
0332
0333 #ifdef CONFIG_HOTPLUG_CPU
0334 static int rockchip_cpu_kill(unsigned int cpu)
0335 {
0336     /*
0337      * We need a delay here to ensure that the dying CPU can finish
0338      * executing v7_coherency_exit() and reach the WFI/WFE state
0339      * prior to having the power domain disabled.
0340      */
0341     mdelay(1);
0342
0343     pmu_set_power_domain(0 + cpu, false);
0344     return 1;
0345 }
0346
0347 static void rockchip_cpu_die(unsigned int cpu)
0348 {
0349     v7_exit_coherency_flush(louis);
0350     while (1)
0351         cpu_do_idle();
0352 }
0353 #endif
0354
0355 static const struct smp_operations rk3036_smp_ops __initconst = {
0356     .smp_prepare_cpus   = rk3036_smp_prepare_cpus,
0357     .smp_boot_secondary = rockchip_boot_secondary,
0358 #ifdef CONFIG_HOTPLUG_CPU
0359     .cpu_kill       = rockchip_cpu_kill,
0360     .cpu_die        = rockchip_cpu_die,
0361 #endif
0362 };
0363
0364 static const struct smp_operations rockchip_smp_ops __initconst = {
0365     .smp_prepare_cpus   = rockchip_smp_prepare_cpus,
0366     .smp_boot_secondary = rockchip_boot_secondary,
0367 #ifdef CONFIG_HOTPLUG_CPU
0368     .cpu_kill       = rockchip_cpu_kill,
0369     .cpu_die        = rockchip_cpu_die,
0370 #endif
0371 };
0372
0373 CPU_METHOD_OF_DECLARE(rk3036_smp, "rockchip,rk3036-smp", &rk3036_smp_ops);
0374 CPU_METHOD_OF_DECLARE(rk3066_smp, "rockchip,rk3066-smp", &rockchip_smp_ops);