arm/mach-pxa/zeus.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  *  arch/arm/mach-pxa/include/mach/zeus.h
0004  *
0005  *  Author: David Vrabel
0006  *  Created:    Sept 28, 2005
0007  *  Copyright:  Arcom Control Systems Ltd.
0008  *
0009  *  Maintained by: Marc Zyngier <maz@misterjones.org>
0010  */
0011
0012 #ifndef _MACH_ZEUS_H
0013 #define _MACH_ZEUS_H
0014
0015 #define ZEUS_NR_IRQS        (IRQ_BOARD_START + 48)
0016
0017 /* Physical addresses */
0018 #define ZEUS_FLASH_PHYS     PXA_CS0_PHYS
0019 #define ZEUS_ETH0_PHYS      PXA_CS1_PHYS
0020 #define ZEUS_ETH1_PHYS      PXA_CS2_PHYS
0021 #define ZEUS_CPLD_PHYS      (PXA_CS4_PHYS+0x2000000)
0022 #define ZEUS_SRAM_PHYS      PXA_CS5_PHYS
0023 #define ZEUS_PC104IO_PHYS   (0x30000000)
0024
0025 #define ZEUS_CPLD_VERSION_PHYS  (ZEUS_CPLD_PHYS + 0x00000000)
0026 #define ZEUS_CPLD_ISA_IRQ_PHYS  (ZEUS_CPLD_PHYS + 0x00800000)
0027 #define ZEUS_CPLD_CONTROL_PHYS  (ZEUS_CPLD_PHYS + 0x01000000)
0028 #define ZEUS_CPLD_EXTWDOG_PHYS  (ZEUS_CPLD_PHYS + 0x01800000)
0029
0030 /* GPIOs */
0031 #define ZEUS_AC97_GPIO      0
0032 #define ZEUS_WAKEUP_GPIO    1
0033 #define ZEUS_UARTA_GPIO     9
0034 #define ZEUS_UARTB_GPIO     10
0035 #define ZEUS_UARTC_GPIO     12
0036 #define ZEUS_UARTD_GPIO     11
0037 #define ZEUS_ETH0_GPIO      14
0038 #define ZEUS_ISA_GPIO       17
0039 #define ZEUS_BKLEN_GPIO     19
0040 #define ZEUS_USB2_PWREN_GPIO    22
0041 #define ZEUS_PTT_GPIO       27
0042 #define ZEUS_CF_CD_GPIO         35
0043 #define ZEUS_MMC_WP_GPIO        52
0044 #define ZEUS_MMC_CD_GPIO        53
0045 #define ZEUS_EXTGPIO_GPIO   91
0046 #define ZEUS_CF_PWEN_GPIO       97
0047 #define ZEUS_CF_RDY_GPIO        99
0048 #define ZEUS_LCD_EN_GPIO    101
0049 #define ZEUS_ETH1_GPIO      113
0050 #define ZEUS_CAN_GPIO       116
0051
0052 #define ZEUS_EXT0_GPIO_BASE 128
0053 #define ZEUS_EXT1_GPIO_BASE 160
0054 #define ZEUS_USER_GPIO_BASE 192
0055
0056 #define ZEUS_EXT0_GPIO(x)   (ZEUS_EXT0_GPIO_BASE + (x))
0057 #define ZEUS_EXT1_GPIO(x)   (ZEUS_EXT1_GPIO_BASE + (x))
0058 #define ZEUS_USER_GPIO(x)   (ZEUS_USER_GPIO_BASE + (x))
0059
0060 #define ZEUS_CAN_SHDN_GPIO  ZEUS_EXT1_GPIO(2)
0061
0062 /*
0063  * CPLD registers:
0064  * Only 4 registers, but spread over a 32MB address space.
0065  * Be gentle, and remap that over 32kB...
0066  */
0067
0068 #define ZEUS_CPLD       IOMEM(0xf0000000)
0069 #define ZEUS_CPLD_VERSION   (ZEUS_CPLD + 0x0000)
0070 #define ZEUS_CPLD_ISA_IRQ   (ZEUS_CPLD + 0x1000)
0071 #define ZEUS_CPLD_CONTROL   (ZEUS_CPLD + 0x2000)
0072
0073 /* CPLD register bits */
0074 #define ZEUS_CPLD_CONTROL_CF_RST        0x01
0075
0076 #define ZEUS_PC104IO        IOMEM(0xf1000000)
0077
0078 #define ZEUS_SRAM_SIZE      (256 * 1024)
0079
0080 #endif
0081
0082