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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  *  Support for the Arcom ZEUS.
0004  *
0005  *  Copyright (C) 2006 Arcom Control Systems Ltd.
0006  *
0007  *  Loosely based on Arcom's 2.6.16.28.
0008  *  Maintained by Marc Zyngier <maz@misterjones.org>
0009  */
0010 
0011 #include <linux/cpufreq.h>
0012 #include <linux/interrupt.h>
0013 #include <linux/leds.h>
0014 #include <linux/irq.h>
0015 #include <linux/pm.h>
0016 #include <linux/property.h>
0017 #include <linux/gpio.h>
0018 #include <linux/gpio/machine.h>
0019 #include <linux/serial_8250.h>
0020 #include <linux/dm9000.h>
0021 #include <linux/mmc/host.h>
0022 #include <linux/spi/spi.h>
0023 #include <linux/spi/pxa2xx_spi.h>
0024 #include <linux/mtd/mtd.h>
0025 #include <linux/mtd/partitions.h>
0026 #include <linux/mtd/physmap.h>
0027 #include <linux/i2c.h>
0028 #include <linux/platform_data/i2c-pxa.h>
0029 #include <linux/platform_data/pca953x.h>
0030 #include <linux/apm-emulation.h>
0031 #include <linux/regulator/fixed.h>
0032 #include <linux/regulator/machine.h>
0033 
0034 #include <asm/mach-types.h>
0035 #include <asm/suspend.h>
0036 #include <asm/system_info.h>
0037 #include <asm/mach/arch.h>
0038 #include <asm/mach/map.h>
0039 
0040 #include "pxa27x.h"
0041 #include "devices.h"
0042 #include "regs-uart.h"
0043 #include <linux/platform_data/usb-ohci-pxa27x.h>
0044 #include <linux/platform_data/mmc-pxamci.h>
0045 #include "pxa27x-udc.h"
0046 #include "udc.h"
0047 #include <linux/platform_data/video-pxafb.h>
0048 #include "pm.h"
0049 #include <linux/platform_data/asoc-pxa.h>
0050 #include "viper-pcmcia.h"
0051 #include "zeus.h"
0052 #include "smemc.h"
0053 
0054 #include "generic.h"
0055 
0056 /*
0057  * Interrupt handling
0058  */
0059 
0060 static unsigned long zeus_irq_enabled_mask;
0061 static const int zeus_isa_irqs[] = { 3, 4, 5, 6, 7, 10, 11, 12, };
0062 static const int zeus_isa_irq_map[] = {
0063     0,      /* ISA irq #0, invalid */
0064     0,      /* ISA irq #1, invalid */
0065     0,      /* ISA irq #2, invalid */
0066     1 << 0,     /* ISA irq #3 */
0067     1 << 1,     /* ISA irq #4 */
0068     1 << 2,     /* ISA irq #5 */
0069     1 << 3,     /* ISA irq #6 */
0070     1 << 4,     /* ISA irq #7 */
0071     0,      /* ISA irq #8, invalid */
0072     0,      /* ISA irq #9, invalid */
0073     1 << 5,     /* ISA irq #10 */
0074     1 << 6,     /* ISA irq #11 */
0075     1 << 7,     /* ISA irq #12 */
0076 };
0077 
0078 static inline int zeus_irq_to_bitmask(unsigned int irq)
0079 {
0080     return zeus_isa_irq_map[irq - PXA_ISA_IRQ(0)];
0081 }
0082 
0083 static inline int zeus_bit_to_irq(int bit)
0084 {
0085     return zeus_isa_irqs[bit] + PXA_ISA_IRQ(0);
0086 }
0087 
0088 static void zeus_ack_irq(struct irq_data *d)
0089 {
0090     __raw_writew(zeus_irq_to_bitmask(d->irq), ZEUS_CPLD_ISA_IRQ);
0091 }
0092 
0093 static void zeus_mask_irq(struct irq_data *d)
0094 {
0095     zeus_irq_enabled_mask &= ~(zeus_irq_to_bitmask(d->irq));
0096 }
0097 
0098 static void zeus_unmask_irq(struct irq_data *d)
0099 {
0100     zeus_irq_enabled_mask |= zeus_irq_to_bitmask(d->irq);
0101 }
0102 
0103 static inline unsigned long zeus_irq_pending(void)
0104 {
0105     return __raw_readw(ZEUS_CPLD_ISA_IRQ) & zeus_irq_enabled_mask;
0106 }
0107 
0108 static void zeus_irq_handler(struct irq_desc *desc)
0109 {
0110     unsigned int irq;
0111     unsigned long pending;
0112 
0113     pending = zeus_irq_pending();
0114     do {
0115         /* we're in a chained irq handler,
0116          * so ack the interrupt by hand */
0117         desc->irq_data.chip->irq_ack(&desc->irq_data);
0118 
0119         if (likely(pending)) {
0120             irq = zeus_bit_to_irq(__ffs(pending));
0121             generic_handle_irq(irq);
0122         }
0123         pending = zeus_irq_pending();
0124     } while (pending);
0125 }
0126 
0127 static struct irq_chip zeus_irq_chip = {
0128     .name       = "ISA",
0129     .irq_ack    = zeus_ack_irq,
0130     .irq_mask   = zeus_mask_irq,
0131     .irq_unmask = zeus_unmask_irq,
0132 };
0133 
0134 static void __init zeus_init_irq(void)
0135 {
0136     int level;
0137     int isa_irq;
0138 
0139     pxa27x_init_irq();
0140 
0141     /* Peripheral IRQs. It would be nice to move those inside driver
0142        configuration, but it is not supported at the moment. */
0143     irq_set_irq_type(gpio_to_irq(ZEUS_AC97_GPIO), IRQ_TYPE_EDGE_RISING);
0144     irq_set_irq_type(gpio_to_irq(ZEUS_WAKEUP_GPIO), IRQ_TYPE_EDGE_RISING);
0145     irq_set_irq_type(gpio_to_irq(ZEUS_PTT_GPIO), IRQ_TYPE_EDGE_RISING);
0146     irq_set_irq_type(gpio_to_irq(ZEUS_EXTGPIO_GPIO),
0147              IRQ_TYPE_EDGE_FALLING);
0148     irq_set_irq_type(gpio_to_irq(ZEUS_CAN_GPIO), IRQ_TYPE_EDGE_FALLING);
0149 
0150     /* Setup ISA IRQs */
0151     for (level = 0; level < ARRAY_SIZE(zeus_isa_irqs); level++) {
0152         isa_irq = zeus_bit_to_irq(level);
0153         irq_set_chip_and_handler(isa_irq, &zeus_irq_chip,
0154                      handle_edge_irq);
0155         irq_clear_status_flags(isa_irq, IRQ_NOREQUEST | IRQ_NOPROBE);
0156     }
0157 
0158     irq_set_irq_type(gpio_to_irq(ZEUS_ISA_GPIO), IRQ_TYPE_EDGE_RISING);
0159     irq_set_chained_handler(gpio_to_irq(ZEUS_ISA_GPIO), zeus_irq_handler);
0160 }
0161 
0162 
0163 /*
0164  * Platform devices
0165  */
0166 
0167 /* Flash */
0168 static struct resource zeus_mtd_resources[] = {
0169     [0] = { /* NOR Flash (up to 64MB) */
0170         .start  = ZEUS_FLASH_PHYS,
0171         .end    = ZEUS_FLASH_PHYS + SZ_64M - 1,
0172         .flags  = IORESOURCE_MEM,
0173     },
0174     [1] = { /* SRAM */
0175         .start  = ZEUS_SRAM_PHYS,
0176         .end    = ZEUS_SRAM_PHYS + SZ_512K - 1,
0177         .flags  = IORESOURCE_MEM,
0178     },
0179 };
0180 
0181 static struct physmap_flash_data zeus_flash_data[] = {
0182     [0] = {
0183         .width      = 2,
0184         .parts      = NULL,
0185         .nr_parts   = 0,
0186     },
0187 };
0188 
0189 static struct platform_device zeus_mtd_devices[] = {
0190     [0] = {
0191         .name       = "physmap-flash",
0192         .id     = 0,
0193         .dev        = {
0194             .platform_data = &zeus_flash_data[0],
0195         },
0196         .resource   = &zeus_mtd_resources[0],
0197         .num_resources  = 1,
0198     },
0199 };
0200 
0201 /* Serial */
0202 static struct resource zeus_serial_resources[] = {
0203     {
0204         .start  = 0x10000000,
0205         .end    = 0x1000000f,
0206         .flags  = IORESOURCE_MEM,
0207     },
0208     {
0209         .start  = 0x10800000,
0210         .end    = 0x1080000f,
0211         .flags  = IORESOURCE_MEM,
0212     },
0213     {
0214         .start  = 0x11000000,
0215         .end    = 0x1100000f,
0216         .flags  = IORESOURCE_MEM,
0217     },
0218     {
0219         .start  = 0x40100000,
0220         .end    = 0x4010001f,
0221         .flags  = IORESOURCE_MEM,
0222     },
0223     {
0224         .start  = 0x40200000,
0225         .end    = 0x4020001f,
0226         .flags  = IORESOURCE_MEM,
0227     },
0228     {
0229         .start  = 0x40700000,
0230         .end    = 0x4070001f,
0231         .flags  = IORESOURCE_MEM,
0232     },
0233 };
0234 
0235 static struct plat_serial8250_port serial_platform_data[] = {
0236     /* External UARTs */
0237     /* FIXME: Shared IRQs on COM1-COM4 will not work properly on v1i1 hardware. */
0238     { /* COM1 */
0239         .mapbase    = 0x10000000,
0240         .irq        = PXA_GPIO_TO_IRQ(ZEUS_UARTA_GPIO),
0241         .irqflags   = IRQF_TRIGGER_RISING,
0242         .uartclk    = 14745600,
0243         .regshift   = 1,
0244         .flags      = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
0245         .iotype     = UPIO_MEM,
0246     },
0247     { /* COM2 */
0248         .mapbase    = 0x10800000,
0249         .irq        = PXA_GPIO_TO_IRQ(ZEUS_UARTB_GPIO),
0250         .irqflags   = IRQF_TRIGGER_RISING,
0251         .uartclk    = 14745600,
0252         .regshift   = 1,
0253         .flags      = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
0254         .iotype     = UPIO_MEM,
0255     },
0256     { /* COM3 */
0257         .mapbase    = 0x11000000,
0258         .irq        = PXA_GPIO_TO_IRQ(ZEUS_UARTC_GPIO),
0259         .irqflags   = IRQF_TRIGGER_RISING,
0260         .uartclk    = 14745600,
0261         .regshift   = 1,
0262         .flags      = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
0263         .iotype     = UPIO_MEM,
0264     },
0265     { /* COM4 */
0266         .mapbase    = 0x11800000,
0267         .irq        = PXA_GPIO_TO_IRQ(ZEUS_UARTD_GPIO),
0268         .irqflags   = IRQF_TRIGGER_RISING,
0269         .uartclk    = 14745600,
0270         .regshift   = 1,
0271         .flags      = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
0272         .iotype     = UPIO_MEM,
0273     },
0274     /* Internal UARTs */
0275     { /* FFUART */
0276         .membase    = (void *)&FFUART,
0277         .mapbase    = __PREG(FFUART),
0278         .irq        = IRQ_FFUART,
0279         .uartclk    = 921600 * 16,
0280         .regshift   = 2,
0281         .flags      = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
0282         .iotype     = UPIO_MEM,
0283     },
0284     { /* BTUART */
0285         .membase    = (void *)&BTUART,
0286         .mapbase    = __PREG(BTUART),
0287         .irq        = IRQ_BTUART,
0288         .uartclk    = 921600 * 16,
0289         .regshift   = 2,
0290         .flags      = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
0291         .iotype     = UPIO_MEM,
0292     },
0293     { /* STUART */
0294         .membase    = (void *)&STUART,
0295         .mapbase    = __PREG(STUART),
0296         .irq        = IRQ_STUART,
0297         .uartclk    = 921600 * 16,
0298         .regshift   = 2,
0299         .flags      = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
0300         .iotype     = UPIO_MEM,
0301     },
0302     { },
0303 };
0304 
0305 static struct platform_device zeus_serial_device = {
0306     .name = "serial8250",
0307     .id   = PLAT8250_DEV_PLATFORM,
0308     .dev  = {
0309         .platform_data = serial_platform_data,
0310     },
0311     .num_resources  = ARRAY_SIZE(zeus_serial_resources),
0312     .resource   = zeus_serial_resources,
0313 };
0314 
0315 /* Ethernet */
0316 static struct resource zeus_dm9k0_resource[] = {
0317     [0] = {
0318         .start = ZEUS_ETH0_PHYS,
0319         .end   = ZEUS_ETH0_PHYS + 1,
0320         .flags = IORESOURCE_MEM
0321     },
0322     [1] = {
0323         .start = ZEUS_ETH0_PHYS + 2,
0324         .end   = ZEUS_ETH0_PHYS + 3,
0325         .flags = IORESOURCE_MEM
0326     },
0327     [2] = {
0328         .start = PXA_GPIO_TO_IRQ(ZEUS_ETH0_GPIO),
0329         .end   = PXA_GPIO_TO_IRQ(ZEUS_ETH0_GPIO),
0330         .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
0331     },
0332 };
0333 
0334 static struct resource zeus_dm9k1_resource[] = {
0335     [0] = {
0336         .start = ZEUS_ETH1_PHYS,
0337         .end   = ZEUS_ETH1_PHYS + 1,
0338         .flags = IORESOURCE_MEM
0339     },
0340     [1] = {
0341         .start = ZEUS_ETH1_PHYS + 2,
0342         .end   = ZEUS_ETH1_PHYS + 3,
0343         .flags = IORESOURCE_MEM,
0344     },
0345     [2] = {
0346         .start = PXA_GPIO_TO_IRQ(ZEUS_ETH1_GPIO),
0347         .end   = PXA_GPIO_TO_IRQ(ZEUS_ETH1_GPIO),
0348         .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
0349     },
0350 };
0351 
0352 static struct dm9000_plat_data zeus_dm9k_platdata = {
0353     .flags      = DM9000_PLATF_16BITONLY,
0354 };
0355 
0356 static struct platform_device zeus_dm9k0_device = {
0357     .name       = "dm9000",
0358     .id     = 0,
0359     .num_resources  = ARRAY_SIZE(zeus_dm9k0_resource),
0360     .resource   = zeus_dm9k0_resource,
0361     .dev        = {
0362         .platform_data = &zeus_dm9k_platdata,
0363     }
0364 };
0365 
0366 static struct platform_device zeus_dm9k1_device = {
0367     .name       = "dm9000",
0368     .id     = 1,
0369     .num_resources  = ARRAY_SIZE(zeus_dm9k1_resource),
0370     .resource   = zeus_dm9k1_resource,
0371     .dev        = {
0372         .platform_data = &zeus_dm9k_platdata,
0373     }
0374 };
0375 
0376 /* External SRAM */
0377 static struct resource zeus_sram_resource = {
0378     .start      = ZEUS_SRAM_PHYS,
0379     .end        = ZEUS_SRAM_PHYS + ZEUS_SRAM_SIZE * 2 - 1,
0380     .flags      = IORESOURCE_MEM,
0381 };
0382 
0383 static struct platform_device zeus_sram_device = {
0384     .name       = "pxa2xx-8bit-sram",
0385     .id     = 0,
0386     .num_resources  = 1,
0387     .resource   = &zeus_sram_resource,
0388 };
0389 
0390 /* SPI interface on SSP3 */
0391 static struct pxa2xx_spi_controller pxa2xx_spi_ssp3_master_info = {
0392     .num_chipselect = 1,
0393     .enable_dma     = 1,
0394 };
0395 
0396 /* CAN bus on SPI */
0397 static struct regulator_consumer_supply can_regulator_consumer =
0398     REGULATOR_SUPPLY("vdd", "spi3.0");
0399 
0400 static struct regulator_init_data can_regulator_init_data = {
0401     .constraints    = {
0402         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
0403     },
0404     .consumer_supplies  = &can_regulator_consumer,
0405     .num_consumer_supplies  = 1,
0406 };
0407 
0408 static struct fixed_voltage_config can_regulator_pdata = {
0409     .supply_name    = "CAN_SHDN",
0410     .microvolts = 3300000,
0411     .init_data  = &can_regulator_init_data,
0412 };
0413 
0414 static struct platform_device can_regulator_device = {
0415     .name   = "reg-fixed-voltage",
0416     .id = 0,
0417     .dev    = {
0418         .platform_data  = &can_regulator_pdata,
0419     },
0420 };
0421 
0422 static struct gpiod_lookup_table can_regulator_gpiod_table = {
0423     .dev_id = "reg-fixed-voltage.0",
0424     .table = {
0425         GPIO_LOOKUP("gpio-pxa", ZEUS_CAN_SHDN_GPIO,
0426                 NULL, GPIO_ACTIVE_LOW),
0427         { },
0428     },
0429 };
0430 
0431 static const struct property_entry mcp251x_properties[] = {
0432     PROPERTY_ENTRY_U32("clock-frequency", 16000000),
0433     {}
0434 };
0435 
0436 static const struct software_node mcp251x_node = {
0437     .properties = mcp251x_properties,
0438 };
0439 
0440 static struct spi_board_info zeus_spi_board_info[] = {
0441     [0] = {
0442         .modalias   = "mcp2515",
0443         .swnode     = &mcp251x_node,
0444         .irq        = PXA_GPIO_TO_IRQ(ZEUS_CAN_GPIO),
0445         .max_speed_hz   = 1*1000*1000,
0446         .bus_num    = 3,
0447         .mode       = SPI_MODE_0,
0448         .chip_select    = 0,
0449     },
0450 };
0451 
0452 /* Leds */
0453 static struct gpio_led zeus_leds[] = {
0454     [0] = {
0455         .name        = "zeus:yellow:1",
0456         .default_trigger = "heartbeat",
0457         .gpio        = ZEUS_EXT0_GPIO(3),
0458         .active_low  = 1,
0459     },
0460     [1] = {
0461         .name        = "zeus:yellow:2",
0462         .default_trigger = "default-on",
0463         .gpio        = ZEUS_EXT0_GPIO(4),
0464         .active_low  = 1,
0465     },
0466     [2] = {
0467         .name        = "zeus:yellow:3",
0468         .default_trigger = "default-on",
0469         .gpio        = ZEUS_EXT0_GPIO(5),
0470         .active_low  = 1,
0471     },
0472 };
0473 
0474 static struct gpio_led_platform_data zeus_leds_info = {
0475     .leds       = zeus_leds,
0476     .num_leds   = ARRAY_SIZE(zeus_leds),
0477 };
0478 
0479 static struct platform_device zeus_leds_device = {
0480     .name       = "leds-gpio",
0481     .id     = -1,
0482     .dev        = {
0483         .platform_data  = &zeus_leds_info,
0484     },
0485 };
0486 
0487 static void zeus_cf_reset(int state)
0488 {
0489     u16 cpld_state = __raw_readw(ZEUS_CPLD_CONTROL);
0490 
0491     if (state)
0492         cpld_state |= ZEUS_CPLD_CONTROL_CF_RST;
0493     else
0494         cpld_state &= ~ZEUS_CPLD_CONTROL_CF_RST;
0495 
0496     __raw_writew(cpld_state, ZEUS_CPLD_CONTROL);
0497 }
0498 
0499 static struct arcom_pcmcia_pdata zeus_pcmcia_info = {
0500     .cd_gpio    = ZEUS_CF_CD_GPIO,
0501     .rdy_gpio   = ZEUS_CF_RDY_GPIO,
0502     .pwr_gpio   = ZEUS_CF_PWEN_GPIO,
0503     .reset      = zeus_cf_reset,
0504 };
0505 
0506 static struct platform_device zeus_pcmcia_device = {
0507     .name       = "zeus-pcmcia",
0508     .id     = -1,
0509     .dev        = {
0510         .platform_data  = &zeus_pcmcia_info,
0511     },
0512 };
0513 
0514 static struct resource zeus_max6369_resource = {
0515     .start      = ZEUS_CPLD_EXTWDOG_PHYS,
0516     .end        = ZEUS_CPLD_EXTWDOG_PHYS,
0517     .flags      = IORESOURCE_MEM,
0518 };
0519 
0520 struct platform_device zeus_max6369_device = {
0521     .name       = "max6369_wdt",
0522     .id     = -1,
0523     .resource   = &zeus_max6369_resource,
0524     .num_resources  = 1,
0525 };
0526 
0527 /* AC'97 */
0528 static pxa2xx_audio_ops_t zeus_ac97_info = {
0529     .reset_gpio = 95,
0530 };
0531 
0532 
0533 /*
0534  * USB host
0535  */
0536 
0537 static struct regulator_consumer_supply zeus_ohci_regulator_supplies[] = {
0538     REGULATOR_SUPPLY("vbus2", "pxa27x-ohci"),
0539 };
0540 
0541 static struct regulator_init_data zeus_ohci_regulator_data = {
0542     .constraints = {
0543         .valid_ops_mask     = REGULATOR_CHANGE_STATUS,
0544     },
0545     .num_consumer_supplies  = ARRAY_SIZE(zeus_ohci_regulator_supplies),
0546     .consumer_supplies  = zeus_ohci_regulator_supplies,
0547 };
0548 
0549 static struct fixed_voltage_config zeus_ohci_regulator_config = {
0550     .supply_name        = "vbus2",
0551     .microvolts     = 5000000, /* 5.0V */
0552     .startup_delay      = 0,
0553     .init_data      = &zeus_ohci_regulator_data,
0554 };
0555 
0556 static struct platform_device zeus_ohci_regulator_device = {
0557     .name       = "reg-fixed-voltage",
0558     .id     = 1,
0559     .dev = {
0560         .platform_data = &zeus_ohci_regulator_config,
0561     },
0562 };
0563 
0564 static struct gpiod_lookup_table zeus_ohci_regulator_gpiod_table = {
0565     .dev_id = "reg-fixed-voltage.0",
0566     .table = {
0567         GPIO_LOOKUP("gpio-pxa", ZEUS_USB2_PWREN_GPIO,
0568                 NULL, GPIO_ACTIVE_HIGH),
0569         { },
0570     },
0571 };
0572 
0573 static struct pxaohci_platform_data zeus_ohci_platform_data = {
0574     .port_mode  = PMM_NPS_MODE,
0575     /* Clear Power Control Polarity Low and set Power Sense
0576      * Polarity Low. Supply power to USB ports. */
0577     .flags      = ENABLE_PORT_ALL | POWER_SENSE_LOW,
0578 };
0579 
0580 static void __init zeus_register_ohci(void)
0581 {
0582     /* Port 2 is shared between host and client interface. */
0583     UP2OCR = UP2OCR_HXOE | UP2OCR_HXS | UP2OCR_DMPDE | UP2OCR_DPPDE;
0584 
0585     pxa_set_ohci_info(&zeus_ohci_platform_data);
0586 }
0587 
0588 /*
0589  * Flat Panel
0590  */
0591 
0592 static void zeus_lcd_power(int on, struct fb_var_screeninfo *si)
0593 {
0594     gpio_set_value(ZEUS_LCD_EN_GPIO, on);
0595 }
0596 
0597 static void zeus_backlight_power(int on)
0598 {
0599     gpio_set_value(ZEUS_BKLEN_GPIO, on);
0600 }
0601 
0602 static int zeus_setup_fb_gpios(void)
0603 {
0604     int err;
0605 
0606     if ((err = gpio_request(ZEUS_LCD_EN_GPIO, "LCD_EN")))
0607         goto out_err;
0608 
0609     if ((err = gpio_direction_output(ZEUS_LCD_EN_GPIO, 0)))
0610         goto out_err_lcd;
0611 
0612     if ((err = gpio_request(ZEUS_BKLEN_GPIO, "BKLEN")))
0613         goto out_err_lcd;
0614 
0615     if ((err = gpio_direction_output(ZEUS_BKLEN_GPIO, 0)))
0616         goto out_err_bkl;
0617 
0618     return 0;
0619 
0620 out_err_bkl:
0621     gpio_free(ZEUS_BKLEN_GPIO);
0622 out_err_lcd:
0623     gpio_free(ZEUS_LCD_EN_GPIO);
0624 out_err:
0625     return err;
0626 }
0627 
0628 static struct pxafb_mode_info zeus_fb_mode_info[] = {
0629     {
0630         .pixclock       = 39722,
0631 
0632         .xres           = 640,
0633         .yres           = 480,
0634 
0635         .bpp            = 16,
0636 
0637         .hsync_len      = 63,
0638         .left_margin    = 16,
0639         .right_margin   = 81,
0640 
0641         .vsync_len      = 2,
0642         .upper_margin   = 12,
0643         .lower_margin   = 31,
0644 
0645         .sync       = 0,
0646     },
0647 };
0648 
0649 static struct pxafb_mach_info zeus_fb_info = {
0650     .modes          = zeus_fb_mode_info,
0651     .num_modes      = 1,
0652     .lcd_conn       = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL,
0653     .pxafb_lcd_power    = zeus_lcd_power,
0654     .pxafb_backlight_power  = zeus_backlight_power,
0655 };
0656 
0657 /*
0658  * MMC/SD Device
0659  *
0660  * The card detect interrupt isn't debounced so we delay it by 250ms
0661  * to give the card a chance to fully insert/eject.
0662  */
0663 
0664 static struct pxamci_platform_data zeus_mci_platform_data = {
0665     .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
0666     .detect_delay_ms    = 250,
0667     .gpio_card_ro_invert    = 1,
0668 };
0669 
0670 static struct gpiod_lookup_table zeus_mci_gpio_table = {
0671     .dev_id = "pxa2xx-mci.0",
0672     .table = {
0673         GPIO_LOOKUP("gpio-pxa", ZEUS_MMC_CD_GPIO,
0674                 "cd", GPIO_ACTIVE_LOW),
0675         GPIO_LOOKUP("gpio-pxa", ZEUS_MMC_WP_GPIO,
0676                 "wp", GPIO_ACTIVE_HIGH),
0677         { },
0678     },
0679 };
0680 
0681 /*
0682  * USB Device Controller
0683  */
0684 static void zeus_udc_command(int cmd)
0685 {
0686     switch (cmd) {
0687     case PXA2XX_UDC_CMD_DISCONNECT:
0688         pr_info("zeus: disconnecting USB client\n");
0689         UP2OCR = UP2OCR_HXOE | UP2OCR_HXS | UP2OCR_DMPDE | UP2OCR_DPPDE;
0690         break;
0691 
0692     case PXA2XX_UDC_CMD_CONNECT:
0693         pr_info("zeus: connecting USB client\n");
0694         UP2OCR = UP2OCR_HXOE | UP2OCR_DPPUE;
0695         break;
0696     }
0697 }
0698 
0699 static struct pxa2xx_udc_mach_info zeus_udc_info = {
0700     .udc_command = zeus_udc_command,
0701 };
0702 
0703 static struct platform_device *zeus_devices[] __initdata = {
0704     &zeus_serial_device,
0705     &zeus_mtd_devices[0],
0706     &zeus_dm9k0_device,
0707     &zeus_dm9k1_device,
0708     &zeus_sram_device,
0709     &zeus_leds_device,
0710     &zeus_pcmcia_device,
0711     &zeus_max6369_device,
0712     &can_regulator_device,
0713     &zeus_ohci_regulator_device,
0714 };
0715 
0716 #ifdef CONFIG_PM
0717 static void zeus_power_off(void)
0718 {
0719     local_irq_disable();
0720     cpu_suspend(PWRMODE_DEEPSLEEP, pxa27x_finish_suspend);
0721 }
0722 #else
0723 #define zeus_power_off   NULL
0724 #endif
0725 
0726 #ifdef CONFIG_APM_EMULATION
0727 static void zeus_get_power_status(struct apm_power_info *info)
0728 {
0729     /* Power supply is always present */
0730     info->ac_line_status    = APM_AC_ONLINE;
0731     info->battery_status    = APM_BATTERY_STATUS_NOT_PRESENT;
0732     info->battery_flag  = APM_BATTERY_FLAG_NOT_PRESENT;
0733 }
0734 
0735 static inline void zeus_setup_apm(void)
0736 {
0737     apm_get_power_status = zeus_get_power_status;
0738 }
0739 #else
0740 static inline void zeus_setup_apm(void)
0741 {
0742 }
0743 #endif
0744 
0745 static int zeus_get_pcb_info(struct i2c_client *client, unsigned gpio,
0746                  unsigned ngpio, void *context)
0747 {
0748     int i;
0749     u8 pcb_info = 0;
0750 
0751     for (i = 0; i < 8; i++) {
0752         int pcb_bit = gpio + i + 8;
0753 
0754         if (gpio_request(pcb_bit, "pcb info")) {
0755             dev_err(&client->dev, "Can't request pcb info %d\n", i);
0756             continue;
0757         }
0758 
0759         if (gpio_direction_input(pcb_bit)) {
0760             dev_err(&client->dev, "Can't read pcb info %d\n", i);
0761             gpio_free(pcb_bit);
0762             continue;
0763         }
0764 
0765         pcb_info |= !!gpio_get_value(pcb_bit) << i;
0766 
0767         gpio_free(pcb_bit);
0768     }
0769 
0770     dev_info(&client->dev, "Zeus PCB version %d issue %d\n",
0771          pcb_info >> 4, pcb_info & 0xf);
0772 
0773     return 0;
0774 }
0775 
0776 static struct pca953x_platform_data zeus_pca953x_pdata[] = {
0777     [0] = { .gpio_base  = ZEUS_EXT0_GPIO_BASE, },
0778     [1] = {
0779         .gpio_base  = ZEUS_EXT1_GPIO_BASE,
0780         .setup      = zeus_get_pcb_info,
0781     },
0782     [2] = { .gpio_base = ZEUS_USER_GPIO_BASE, },
0783 };
0784 
0785 static struct i2c_board_info __initdata zeus_i2c_devices[] = {
0786     {
0787         I2C_BOARD_INFO("pca9535",   0x21),
0788         .platform_data  = &zeus_pca953x_pdata[0],
0789     },
0790     {
0791         I2C_BOARD_INFO("pca9535",   0x22),
0792         .platform_data  = &zeus_pca953x_pdata[1],
0793     },
0794     {
0795         I2C_BOARD_INFO("pca9535",   0x20),
0796         .platform_data  = &zeus_pca953x_pdata[2],
0797         .irq        = PXA_GPIO_TO_IRQ(ZEUS_EXTGPIO_GPIO),
0798     },
0799     { I2C_BOARD_INFO("lm75a",   0x48) },
0800     { I2C_BOARD_INFO("24c01",   0x50) },
0801     { I2C_BOARD_INFO("isl1208", 0x6f) },
0802 };
0803 
0804 static mfp_cfg_t zeus_pin_config[] __initdata = {
0805     /* AC97 */
0806     GPIO28_AC97_BITCLK,
0807     GPIO29_AC97_SDATA_IN_0,
0808     GPIO30_AC97_SDATA_OUT,
0809     GPIO31_AC97_SYNC,
0810 
0811     GPIO15_nCS_1,
0812     GPIO78_nCS_2,
0813     GPIO80_nCS_4,
0814     GPIO33_nCS_5,
0815 
0816     GPIO22_GPIO,
0817     GPIO32_MMC_CLK,
0818     GPIO92_MMC_DAT_0,
0819     GPIO109_MMC_DAT_1,
0820     GPIO110_MMC_DAT_2,
0821     GPIO111_MMC_DAT_3,
0822     GPIO112_MMC_CMD,
0823 
0824     GPIO88_USBH1_PWR,
0825     GPIO89_USBH1_PEN,
0826     GPIO119_USBH2_PWR,
0827     GPIO120_USBH2_PEN,
0828 
0829     GPIO86_LCD_LDD_16,
0830     GPIO87_LCD_LDD_17,
0831 
0832     GPIO102_GPIO,
0833     GPIO104_CIF_DD_2,
0834     GPIO105_CIF_DD_1,
0835 
0836     GPIO81_SSP3_TXD,
0837     GPIO82_SSP3_RXD,
0838     GPIO83_SSP3_SFRM,
0839     GPIO84_SSP3_SCLK,
0840 
0841     GPIO48_nPOE,
0842     GPIO49_nPWE,
0843     GPIO50_nPIOR,
0844     GPIO51_nPIOW,
0845     GPIO85_nPCE_1,
0846     GPIO54_nPCE_2,
0847     GPIO79_PSKTSEL,
0848     GPIO55_nPREG,
0849     GPIO56_nPWAIT,
0850     GPIO57_nIOIS16,
0851     GPIO36_GPIO,        /* CF CD */
0852     GPIO97_GPIO,        /* CF PWREN */
0853     GPIO99_GPIO,        /* CF RDY */
0854 };
0855 
0856 /*
0857  * DM9k MSCx settings:  SRAM, 16 bits
0858  *          17 cycles delay first access
0859  *           5 cycles delay next access
0860  *          13 cycles recovery time
0861  *          faster device
0862  */
0863 #define DM9K_MSC_VALUE      0xe4c9
0864 
0865 static void __init zeus_init(void)
0866 {
0867     u16 dm9000_msc = DM9K_MSC_VALUE;
0868     u32 msc0, msc1;
0869 
0870     system_rev = __raw_readw(ZEUS_CPLD_VERSION);
0871     pr_info("Zeus CPLD V%dI%d\n", (system_rev & 0xf0) >> 4, (system_rev & 0x0f));
0872 
0873     /* Fix timings for dm9000s (CS1/CS2)*/
0874     msc0 = (__raw_readl(MSC0) & 0x0000ffff) | (dm9000_msc << 16);
0875     msc1 = (__raw_readl(MSC1) & 0xffff0000) | dm9000_msc;
0876     __raw_writel(msc0, MSC0);
0877     __raw_writel(msc1, MSC1);
0878 
0879     pm_power_off = zeus_power_off;
0880     zeus_setup_apm();
0881 
0882     pxa2xx_mfp_config(ARRAY_AND_SIZE(zeus_pin_config));
0883 
0884     gpiod_add_lookup_table(&can_regulator_gpiod_table);
0885     gpiod_add_lookup_table(&zeus_ohci_regulator_gpiod_table);
0886     platform_add_devices(zeus_devices, ARRAY_SIZE(zeus_devices));
0887 
0888     zeus_register_ohci();
0889 
0890     if (zeus_setup_fb_gpios())
0891         pr_err("Failed to setup fb gpios\n");
0892     else
0893         pxa_set_fb_info(NULL, &zeus_fb_info);
0894 
0895     gpiod_add_lookup_table(&zeus_mci_gpio_table);
0896     pxa_set_mci_info(&zeus_mci_platform_data);
0897     pxa_set_udc_info(&zeus_udc_info);
0898     pxa_set_ac97_info(&zeus_ac97_info);
0899     pxa_set_i2c_info(NULL);
0900     i2c_register_board_info(0, ARRAY_AND_SIZE(zeus_i2c_devices));
0901     pxa2xx_set_spi_info(3, &pxa2xx_spi_ssp3_master_info);
0902     spi_register_board_info(zeus_spi_board_info, ARRAY_SIZE(zeus_spi_board_info));
0903 
0904     regulator_has_full_constraints();
0905 }
0906 
0907 static struct map_desc zeus_io_desc[] __initdata = {
0908     {
0909         .virtual = (unsigned long)ZEUS_CPLD_VERSION,
0910         .pfn     = __phys_to_pfn(ZEUS_CPLD_VERSION_PHYS),
0911         .length  = 0x1000,
0912         .type    = MT_DEVICE,
0913     },
0914     {
0915         .virtual = (unsigned long)ZEUS_CPLD_ISA_IRQ,
0916         .pfn     = __phys_to_pfn(ZEUS_CPLD_ISA_IRQ_PHYS),
0917         .length  = 0x1000,
0918         .type    = MT_DEVICE,
0919     },
0920     {
0921         .virtual = (unsigned long)ZEUS_CPLD_CONTROL,
0922         .pfn     = __phys_to_pfn(ZEUS_CPLD_CONTROL_PHYS),
0923         .length  = 0x1000,
0924         .type    = MT_DEVICE,
0925     },
0926     {
0927         .virtual = (unsigned long)ZEUS_PC104IO,
0928         .pfn     = __phys_to_pfn(ZEUS_PC104IO_PHYS),
0929         .length  = 0x00800000,
0930         .type    = MT_DEVICE,
0931     },
0932     {
0933         /*
0934          * ISA I/O space mapping:
0935          * -  ports 0x0000-0x0fff are PC/104
0936          * -  ports 0x10000-0x10fff are PCMCIA slot 1
0937          * -  ports 0x11000-0x11fff are PC/104
0938          */
0939         .virtual = PCI_IO_VIRT_BASE,
0940         .pfn     = __phys_to_pfn(ZEUS_PC104IO_PHYS),
0941         .length  = 0x1000,
0942         .type    = MT_DEVICE,
0943     },
0944 };
0945 
0946 static void __init zeus_map_io(void)
0947 {
0948     pxa27x_map_io();
0949 
0950     iotable_init(zeus_io_desc, ARRAY_SIZE(zeus_io_desc));
0951 
0952     /* Clear PSPR to ensure a full restart on wake-up. */
0953     PMCR = PSPR = 0;
0954 
0955     /* enable internal 32.768Khz oscillator (ignore OSCC_OOK) */
0956     writel(readl(OSCC) | OSCC_OON, OSCC);
0957 
0958     /* Some clock cycles later (from OSCC_ON), programme PCFR (OPDE...).
0959      * float chip selects and PCMCIA */
0960     PCFR = PCFR_OPDE | PCFR_DC_EN | PCFR_FS | PCFR_FP;
0961 }
0962 
0963 MACHINE_START(ARCOM_ZEUS, "Arcom/Eurotech ZEUS")
0964     /* Maintainer: Marc Zyngier <maz@misterjones.org> */
0965     .atag_offset    = 0x100,
0966     .map_io     = zeus_map_io,
0967     .nr_irqs    = ZEUS_NR_IRQS,
0968     .init_irq   = zeus_init_irq,
0969     .handle_irq = pxa27x_handle_irq,
0970     .init_time  = pxa_timer_init,
0971     .init_machine   = zeus_init,
0972     .restart    = pxa_restart,
0973 MACHINE_END
0974
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