arm/mach-pxa/viper.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * arch/arm/mach-pxa/include/mach/viper.h
0004  *
0005  * Author:  Ian Campbell
0006  * Created: Feb 03, 2003
0007  * Copyright:   Arcom Control Systems.
0008  *
0009  * Maintained by Marc Zyngier <maz@misterjones.org>
0010  *                <marc.zyngier@altran.com>
0011  *
0012  * Created based on lubbock.h:
0013  *  Author: Nicolas Pitre
0014  *  Created:    Jun 15, 2001
0015  *  Copyright:  MontaVista Software Inc.
0016  */
0017
0018 #ifndef ARCH_VIPER_H
0019 #define ARCH_VIPER_H
0020
0021 #define VIPER_BOOT_PHYS     PXA_CS0_PHYS
0022 #define VIPER_FLASH_PHYS    PXA_CS1_PHYS
0023 #define VIPER_ETH_PHYS      PXA_CS2_PHYS
0024 #define VIPER_USB_PHYS      PXA_CS3_PHYS
0025 #define VIPER_ETH_DATA_PHYS PXA_CS4_PHYS
0026 #define VIPER_CPLD_PHYS     PXA_CS5_PHYS
0027
0028 #define VIPER_CPLD_BASE     (0xf0000000)
0029 #define VIPER_PC104IO_BASE  (0xf1000000)
0030 #define VIPER_USB_BASE      (0xf1800000)
0031
0032 #define VIPER_ETH_GPIO      (0)
0033 #define VIPER_CPLD_GPIO     (1)
0034 #define VIPER_USB_GPIO      (2)
0035 #define VIPER_UARTA_GPIO    (4)
0036 #define VIPER_UARTB_GPIO    (3)
0037 #define VIPER_CF_CD_GPIO    (32)
0038 #define VIPER_CF_RDY_GPIO   (8)
0039 #define VIPER_BCKLIGHT_EN_GPIO  (9)
0040 #define VIPER_LCD_EN_GPIO   (10)
0041 #define VIPER_PSU_DATA_GPIO (6)
0042 #define VIPER_PSU_CLK_GPIO  (11)
0043 #define VIPER_UART_SHDN_GPIO    (12)
0044 #define VIPER_BRIGHTNESS_GPIO   (16)
0045 #define VIPER_PSU_nCS_LD_GPIO   (19)
0046 #define VIPER_UPS_GPIO      (20)
0047 #define VIPER_CF_POWER_GPIO (82)
0048 #define VIPER_TPM_I2C_SDA_GPIO  (26)
0049 #define VIPER_TPM_I2C_SCL_GPIO  (27)
0050 #define VIPER_RTC_I2C_SDA_GPIO  (83)
0051 #define VIPER_RTC_I2C_SCL_GPIO  (84)
0052
0053 #define VIPER_CPLD_P2V(x)   ((x) - VIPER_CPLD_PHYS + VIPER_CPLD_BASE)
0054 #define VIPER_CPLD_V2P(x)   ((x) - VIPER_CPLD_BASE + VIPER_CPLD_PHYS)
0055
0056 #ifndef __ASSEMBLY__
0057 #  define __VIPER_CPLD_REG(x)   (*((volatile u16 *)VIPER_CPLD_P2V(x)))
0058 #endif
0059
0060 /* board level registers in the CPLD: (offsets from CPLD_BASE) ... */
0061
0062 /* ... Physical addresses */
0063 #define _VIPER_LO_IRQ_STATUS    (VIPER_CPLD_PHYS + 0x100000)
0064 #define _VIPER_ICR_PHYS     (VIPER_CPLD_PHYS + 0x100002)
0065 #define _VIPER_HI_IRQ_STATUS    (VIPER_CPLD_PHYS + 0x100004)
0066 #define _VIPER_VERSION_PHYS (VIPER_CPLD_PHYS + 0x100006)
0067 #define VIPER_UARTA_PHYS    (VIPER_CPLD_PHYS + 0x300010)
0068 #define VIPER_UARTB_PHYS    (VIPER_CPLD_PHYS + 0x300000)
0069 #define _VIPER_SRAM_BASE    (VIPER_CPLD_PHYS + 0x800000)
0070
0071 /* ... Virtual addresses */
0072 #define VIPER_LO_IRQ_STATUS __VIPER_CPLD_REG(_VIPER_LO_IRQ_STATUS)
0073 #define VIPER_HI_IRQ_STATUS __VIPER_CPLD_REG(_VIPER_HI_IRQ_STATUS)
0074 #define VIPER_VERSION       __VIPER_CPLD_REG(_VIPER_VERSION_PHYS)
0075 #define VIPER_ICR       __VIPER_CPLD_REG(_VIPER_ICR_PHYS)
0076
0077 /* Decode VIPER_VERSION register */
0078 #define VIPER_CPLD_REVISION(x)  (((x) >> 5) & 0x7)
0079 #define VIPER_BOARD_VERSION(x)  (((x) >> 3) & 0x3)
0080 #define VIPER_BOARD_ISSUE(x)    (((x) >> 0) & 0x7)
0081
0082 /* Interrupt and Configuration Register (VIPER_ICR) */
0083 /* This is a write only register. Only CF_RST is used under Linux */
0084
0085 #define VIPER_ICR_RETRIG    (1 << 0)
0086 #define VIPER_ICR_AUTO_CLR  (1 << 1)
0087 #define VIPER_ICR_R_DIS     (1 << 2)
0088 #define VIPER_ICR_CF_RST    (1 << 3)
0089
0090 #endif
0091